# US 12,113,116 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,113,116 B2
- Document ID: US12113116B2
- Status: Granted
- Kind: B2
- Application number: 18/352,876
- Filed: 2023-07-14
- Published: 2024-01-18
- Granted: 2024-10-08
- Earliest claimed: 2020-07-31
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.; National Taiwan University
- Inventors: Hsien-Wen Wan; Yi-Ting Cheng; Ming-Hwei Hong; Juei-Nai Kwo; Bo-Yu Yang; Yu-Jie Hong
- Web page: https://patentgrep.com/patent/US12113116B2

## CPC

- H10D 64/685: {being perpendicular to the channel plane}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a semiconductor fin over the substrate;
a semiconductive protection layer over the semiconductor fin;
a gate structure over the semiconductive protection layer, wherein the gate structure comprises:
an interfacial layer over the semiconductive protection layer, wherein the interfacial layer is an oxide of the semiconductive protection layer;
a high-k dielectric layer over the interfacial layer; and
a gate electrode over the high-k dielectric layer;
gate spacers on opposite sidewalls of the gate structure, wherein the semiconductive protection layer and the interfacial layer are in contact with the gate spacers; and
source/drain structures on opposite sides of the gate structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the high-k dielectric layer is in contact with the gate spacers.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductive protection layer and the interfacial layer both include a bar-shape cross-section.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the high-k dielectric layer includes a U-shape cross-section.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a shallow trench isolation (STI) region laterally surrounding the semiconductor fin, wherein the semiconductive protection layer and the interfacial layer are in contact with the STI region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the high-k dielectric layer is in contact with the STI region.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductive protection layer is thicker than the interfacial layer.

### Claim 8

A semiconductor device, comprising:
a substrate;
a semiconductor fin over the substrate;
a shallow trench isolation (STI) structure laterally surrounding the semiconductor fin;
a semiconductor layer crossing the semiconductor fin;
a gate structure over the semiconductor fin, wherein the gate structure comprises:
an interfacial layer over the semiconductor layer;
a gate dielectric layer over the interfacial layer, wherein the semiconductor layer, the interfacial layer, and the gate dielectric layer are in contact with the STI structure; and
a gate electrode over the gate dielectric layer;
gate spacers on opposite sidewalls of the gate structure, wherein the semiconductor layer and the interfacial layer are in contact with the gate spacers; and
source/drain structures on opposite sides of the gate structure.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the semiconductor layer is thicker than the interfacial layer.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the interfacial layer is an oxide of the semiconductor layer.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the interfacial layer is spaced apart from the semiconductor fin through the semiconductor layer.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein an oxygen concentration of the gate dielectric layer decreases in a direction from the gate electrode toward the interfacial layer.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the semiconductor layer is made of silicon.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the gate dielectric layer is in contact with the gate spacers.

### Claim 15

A semiconductor device, comprising:
a germanium substrate;
a silicon cap over the germanium substrate;
a gate structure over the silicon cap, wherein the gate structure comprises:
an oxide layer over the silicon cap;
a high-k dielectric layer over the oxide layer; and
a gate electrode over the high-k dielectric layer;
gate spacers on opposite sidewalls of the gate structure; and
source/drain structures on opposite sides of the gate structure.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the oxide layer is an oxide of the silicon cap.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein in a cross-sectional view, a bottom surface of the oxide layer is higher than bottom surfaces of the gate spacers.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the silicon cap, the oxide layer, and the high-k dielectric layer are in contact with the gate spacers.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the silicon cap and the oxide layer both include a bar-shape cross-section, and the high-k dielectric layer includes a U-shape cross-section.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the silicon cap is thicker than the oxide layer.