# US 12,113,115 B2 · Thin film transistor including a compositionally-graded gate dielectric and methods for forming the same

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- Number: US 12,113,115 B2
- Document ID: US12113115B2
- Status: Granted
- Kind: B2
- Application number: 17/467,497
- Filed: 2021-09-07
- Published: 2022-08-11
- Granted: 2024-10-08
- Earliest claimed: 2021-02-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Wu-Wei Tsai; Chun-Chieh Lu; Hai-Ching Chen; Yu-Ming Lin; Sai-Hooi Yeong
- Web page: https://patentgrep.com/patent/US12113115B2

## CPC

- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/6306: {of the semiconductor materials}
- H10P 14/6319: {Formation by plasma treatments, e.g. plasma oxidation of the substrate}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10B 53/30: characterised by the memory core region
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 14/3226: {Oxides}
- H10P 14/3234: {being oxide semiconducting materials (Group IIB-VIA semiconductors H10P14/3224)}
- H10P 14/3254: {Graded layers}
- H10P 14/3426: {Oxides}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

## Claims

### Claim 1

A semiconductor device comprising a thin film transistor located over a substrate, wherein the thin film transistor comprises:
an insulating layer embedding a gate electrode and overlying a substrate;
a stack of a gate dielectric and an active layer comprising a semiconducting metal oxide material, the stack overlying the gate electrode; and
a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer, wherein:
the source electrode is in direct contact with a first surface segment of a top surface of the insulating layer, first end portions of a pair of lengthwise sidewalls of the gate dielectric, an entirety of a first widthwise sidewall of the gate dielectric, first end portions of the pair of lengthwise sidewalls of the active layer, an entirety of a first one of the pair of widthwise sidewalls of the active layer, and a first end segment of the top surface of the active layer; and
the drain electrode is in direct contact with a second surface segment of the top surface of the insulating layer, second end portions of the pair of lengthwise sidewalls of the gate dielectric, an entirety of a second widthwise sidewall of the gate dielectric, second end portions of the pair of lengthwise sidewalls of the active layer, an entirety of a second one of the pair of widthwise sidewalls of the active layer, and a second end segment of the top surface of the active layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a bottom surface portion of the active layer has a compositional gradient such that an atomic concentration of oxygen atoms decreases with a vertical distance upward from the interface at least to 20% of a vertical thickness of the active layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the active layer comprises a compound semiconductor material including at least two metallic elements and oxygen.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein:
the active layer comprises an indium gallium zinc oxide material; and
oxygen deficiency within the active layer increases with the vertical distance upward from the interface at least to 20% of the vertical thickness of the active layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the compositionally-graded dielectric metal oxide material is selected from aluminum oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, a compound thereof, and a layer stack thereof.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a top gate dielectric contacting a portion of a top surface of the active layer, portions of the pair of lengthwise sidewalls of the active layer, a segment of a top surface of the gate electrode that does not have an areal overlap with the active layer, and a segment of a top surface of the insulating layer, wherein a pair of sidewalls of the top gate dielectric extends along a direction that is perpendicular to a separation direction between the source electrode and the drain electrode from the segment of the top surface of the gate electrode to the segment of a top surface of the insulating layer; and
a top gate electrode overlying the top gate dielectric and having a pair of sidewalls that are located within a pair of vertical planes that contain the pair of sidewalls of the top gate dielectric.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a top gate dielectric contacting a portion of a top surface of the active layer, portions of the pair of lengthwise sidewalls of the active layer, a segment of a top surface of the gate electrode that does not have an areal overlap with the active layer, and a segment of a top surface of the insulating layer, wherein a pair of sidewalls of the top gate dielectric extends along a direction that is perpendicular to a separation direction between the source electrode and the drain electrode from the segment of the top surface of the gate electrode to the segment of a top surface of the insulating layer; and
a top gate electrode overlying the top gate dielectric and comprising a pair of vertically-extending portions that are vertically spaced from the top surface of the gate electrode by a uniform vertical spacing that equals a thickness of the top gate dielectric.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a dielectric layer overlying the insulating layer and laterally surrounding the stack; and
a backside electrode contact via structure vertically extending through the dielectric layer and contacting a top surface of the gate electrode,
wherein each of the source electrode, the drain electrode, and the backside electrode contact via structure comprises a respective combination of a metallic liner and a metallic fill material portion;
wherein the metallic liners of the source electrode, the drain electrode, and the backside electrode contact via structure has a same material composition and a same thickness; and
wherein the metallic fill material portions of the source electrode, the drain electrode, and the backside electrode contact via structure have a same metallic material composition.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the compositionally graded semiconducting metal oxide region comprises all volumes of the active layer that is spaced from a combination of the top surface, the pair of lengthwise sidewalls, and the pair of widthwise sidewalls.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric comprises a compositionally-graded dielectric metal oxide material which has a top surface that is in direct contact with a bottom surface of the active layer, and has an oxygen concentration gradient therein so that an atomic ratio of oxygen atoms to metal atoms within the compositionally graded dielectric metal oxide material decreases with a vertical distance downward from an interface between the gate dielectric and the active layer.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein:
the active layer comprises a top surface, a pair of lengthwise sidewalls having a pair first top edges that coincide with first edges of the top surface, and a pair of widthwise sidewalls having a pair of second top edges that coincide with second edges of the top surface; and
the semiconducting metal oxide material of the active layer comprises a compositionally graded semiconducting metal oxide region which is a surface portion of the semiconducting metal oxide material that continuously extends underneath the top surface, the pair of lengthwise sidewalls, and the pair of widthwise sidewalls, a bottom surface portion that is located within a distance of 20% of a vertical thickness of the active layer from a top surface of the gate dielectric and inside vertically-extending portions of the compositionally graded semiconducting metal oxide region that underlie the pair of lengthwise sidewalls and the pair of widthwise sidewalls, and a homogeneous semiconducting metal oxide region that is encapsulated by a combination of the compositionally graded semiconducting metal oxide region and the bottom surface portion; wherein the homogeneous semiconducting metal oxide region has a homogeneous material composition throughout.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the compositionally graded semiconducting metal oxide region has an oxygen concentration gradient therein so that, for each volume inside the compositionally graded semiconducting metal oxide region, an atomic ratio of oxygen atoms to metal atoms within the compositionally graded semiconducting metal oxide region decreases with a distance from a most proximal surface among the combination of the top surface, the pair of lengthwise sidewalls, and the pair of widthwise sidewalls.

### Claim 13

A semiconductor device comprising a thin film transistor located over a substrate, wherein the thin film transistor comprises:
a gate electrode overlying a substrate;
a stack of a gate dielectric and an active layer comprising a semiconducting metal oxide material, the stack overlying the gate electrode, wherein the active layer has a substantially uniform thickness throughout between a first horizontal plane including a bottom surface of the active layer and a second horizontal plane including a top surface of the active layer; and
a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer;
a top gate dielectric contacting a portion of a top surface of the active layer, portions of the pair of lengthwise sidewalls of the active layer, a segment of a top surface of the gate electrode that does not have an areal overlap with the active layer, and a segment of a top surface of the insulating layer, wherein a pair of sidewalls of the top gate dielectric extends along a direction that is perpendicular to a separation direction between the source electrode and the drain electrode from the segment of the top surface of the gate electrode to the segment of a top surface of the insulating layer; and
a top gate electrode overlying the top gate dielectric, wherein an entire area of each sidewall of the gate dielectric is directly contacted by the top gate dielectric.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein:
the active layer comprises an indium gallium zinc oxide material; and
oxygen deficiency within the active layer increases with the vertical distance downward from the horizontal plane including the top surface of the active layer at least to 20% of the vertical thickness of the active layer.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein:
the gate dielectric comprises a compositionally-graded gate dielectric material in which an atomic concentration of oxygen atoms within the gate dielectric decreases with a vertical distance downward from an interface between the gate dielectric and the active layer; and
a bottom surface portion of the active layer has a compositional gradient such that an atomic concentration of oxygen atoms decreases with a vertical distance upward from the interface at least to 20% of a vertical thickness of the active layer.

### Claim 16

A semiconductor device comprising a thin film transistor located over a substrate, wherein the thin film transistor comprises:
an insulating layer embedding a gate electrode and overlying a substrate;
a stack of a gate dielectric and an active layer comprising a semiconducting metal oxide material, the stack overlying the gate electrode;
a dielectric layer overlying the insulating layer and laterally surrounding the stack;
a top gate dielectric contacting a portion of a top surface of the active layer, portions of the pair of lengthwise sidewalls of the active layer, a segment of a top surface of the gate electrode that does not have an areal overlap with the active layer, and a segment of a top surface of the insulating layer, wherein a pair of sidewalls of the top gate dielectric extends along a direction that is perpendicular to a separation direction between the source electrode and the drain electrode from the segment of the top surface of the gate electrode to the segment of a top surface of the insulating layer; and
a top gate electrode overlying the top gate dielectric, wherein each of sidewalls of the top gate electrode are vertically coincident with a respective sidewall of the top gate dielectric, and each of the sidewalls of the top gate electrode has a respective bottom edge that coincides with a respective edge of the top gate dielectric.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein:
the compositionally-graded gate dielectric material comprises a compositionally-graded dielectric metal oxide material; and
the compositionally-graded dielectric metal oxide material is selected from aluminum oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, a compound thereof, and a layer stack thereof.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein a top surface portion of the active layer has a compositional gradient such that an atomic concentration of oxygen atoms decreases with a vertical distance downward from a horizontal plane including a top surface of the active layer at least to 20% of a vertical thickness of the active layer.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein:
the active layer comprises an indium gallium zinc oxide material; and
oxygen deficiency within the active layer increases with the vertical distance downward from the horizontal plane including the top surface of the active layer at least to 20% of the vertical thickness of the active layer.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, further comprising a dielectric layer overlying the insulating layer and laterally surrounding the stack, wherein:
each of the sidewalls of the top gate electrode is in direct contact with the dielectric layer or with a respective surface segment of the top gate dielectric; and
each of sidewalls of the top gate dielectric is in direct contact with the dielectric layer, the top gate electrode, the active layer, or the gate dielectric.