# US 12,113,113 B2 · Semiconductor device with a core-shell feature and method for forming the same

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- Number: US 12,113,113 B2
- Document ID: US12113113B2
- Status: Granted
- Kind: B2
- Application number: 17/389,142
- Filed: 2021-07-29
- Published: 2023-02-02
- Granted: 2024-10-08
- Earliest claimed: 2021-07-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Chung Chang; Sung-En Lin; Chung-Ting Ko; You-Ting Lin; Yi-Hsiu Liu; Po-Wei Liang; Jiun-Ming Kuo; Yung-Cheng Lu; Chi On Chui; Yuan-Ching Peng; Jen-Hong Chang
- Web page: https://patentgrep.com/patent/US12113113B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0153: {using gate cut processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers, a dielectric fin extending in parallel to and between the fin structures, and a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers. The dielectric fin includes a fin bottom and a fin top over the fin bottom. The fin bottom has a top surface extending above a bottom surface of a topmost channel layer. The fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.

## Claims

### Claim 1

A semiconductor device, comprising:
a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers;
a dielectric fin extending in parallel to and between the fin structures; and
a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers,
wherein the dielectric fin includes a fin bottom and a fin top over the fin bottom,
wherein the fin bottom has a top surface extending above a bottom surface of a topmost channel layer, and
wherein the fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric material has a k value less than silicon oxide, and the second dielectric material has a k value greater than silicon oxide.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein an average k value of the fin top is about 7 to about 20.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the shell separates the core from contacting the fin bottom.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the shell directly interfaces with the fin bottom.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a ratio of a height dimension of the shell to a width dimension of the shell is about 0.4 to about 3.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the shell is about 0.5 nm to about 5 nm.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a first source/drain feature and a second source/drain feature on both sides of the dielectric fin, wherein a top surface of the first source/drain feature and a top surface of the second source/drain feature each extend between a top surface of the fin top and a bottom surface of the fin top.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure includes two gate portions having different compositions, and the fin top extends above a top surface of the two gate portions.

### Claim 10

A device, comprising:
a semiconductor substrate;
a first stack of channel layers and a second stack of channel layers each vertically arranged above the semiconductor substrate and extending in parallel with each other;
a dielectric fin between the first stack of channel layers and the second stack of channel layers; and
a gate structure extending across a top surface of the first stack of channel layers, the second stack of channel layers, and the dielectric fin,
wherein the dielectric fin includes a fin top having a bottom surface extending along or above a topmost channel layer, and
wherein the fin top includes a first dielectric material surrounding a second dielectric material on at least four sides.

### Claim 11 (depends on 10)

The device of claim 10, wherein the first dielectric material has a k value greater than about 7, and the second dielectric material has a k value less than about 7.

### Claim 12 (depends on 10)

The device of claim 10, wherein a percentage of a volume of the second dielectric material relative to a sum of the volume of the second dielectric material and a volume of the first dielectric material is about 30% to about 80%.

### Claim 13 (depends on 10)

The device of claim 10, wherein the fin top has an average k value of about 7 to about 20.

### Claim 14 (depends on 10)

The device of claim 10, wherein the second dielectric material includes nitrogen and hydrogen.

### Claim 15

A semiconductor device, comprising:
a substrate;
a first plurality of channel layers vertically stacked and suspended above the substrate;
a second plurality of channel layers vertically stacked and suspended above the substrate;
an isolation structure disposed on the substrate and between the first plurality of channel layers and the second plurality of channel layers; and
a dielectric fin disposed on the isolation structure and between the first plurality of channel layers and the second plurality of channel layers,
wherein:
the dielectric fin includes a fin bottom and a fin top,
the fin bottom includes a first outer layer of a first dielectric constant and a first inner layer of a second dielectric constant that is smaller than the first dielectric constant, and
the fin top includes a second outer layer of a third dielectric constant and a second inner layer of a fourth dielectric constant that is smaller than the third dielectric constant.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the fourth dielectric constant is less than the second dielectric constant.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the second inner layer is fully surrounded by the second outer layer in a cross-sectional view perpendicular to a top surface of the substrate.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first inner layer is in physical contact with the second outer layer.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the second inner layer includes silicon and oxygen, and the fourth dielectric constant is less than that of silicon oxide.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, further comprising:
a first epitaxial feature abutting the first plurality of channel layers; and
a second epitaxial feature abutting the second plurality of channel layers,
wherein the first epitaxial feature is spaced apart from the second epitaxial feature with the dielectric fin therebetween.