# US 12,113,112 B2 · Semiconductor device including gate structure and separation structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,112 B2 - Document ID: US12113112B2 - Status: Granted - Kind: B2 - Application number: 18/236,823 - Filed: 2023-08-22 - Published: 2023-12-07 - Granted: 2024-10-08 - Earliest claimed: 2019-05-30 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yongho Jeon; Sekoo Kang; Keunhee Bai; Dongseok Lee - Web page: https://patentgrep.com/patent/US12113112B2 ## CPC - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 64/01: Manufacture or treatment - H10D 64/514: {characterised by the insulating layers} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/834: {comprising FinFETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes first and second gate structures respectively on first and second active regions and an insulating layer between the first and second active regions and a separation structure between a first end portion of the first gate structure and a second end portion of the second gate structure and extending into the insulating layer. The separation structure includes a lower portion, an intermediate portion, and an upper portion, a maximum width of the intermediate portion in the first direction is greater than a maximum width of the lower portion in the first direction, and the maximum width of the intermediate portion is greater than a maximum width of the upper portion in the first direction. ## Claims ### Claim 1 A method of manufacturing a semiconductor device comprising: forming a lower insulating layer on a substrate; forming an intermediate insulating layer on the lower insulating layer; forming a conductive structure on the intermediate insulating layer; forming a preliminary opening penetrating through the conductive structure; forming an opening by partially etching the intermediate insulating layer and the lower insulating layer, after forming the preliminary opening; and forming a separation structure in the opening, wherein the opening divides the conductive structure into a first conductive pattern and a second conductive pattern, wherein the opening divides the intermediate insulating layer into a first intermediate insulating pattern and a second intermediate insulating pattern, wherein the separation structure includes: an intermediate portion between the first intermediate insulating pattern and the second intermediate insulating pattern; an upper portion upwardly extending from the intermediate portion and between the first conductive pattern and the second conductive pattern; and a lower portion downwardly extending from the intermediate portion and within the lower insulating layer, and wherein a maximum width of the intermediate portion is greater than a maximum width of the lower portion. ### Claim 2 (depends on 1) The method of manufacturing a semiconductor device of claim 1, wherein a thickness of the lower insulating layer is greater than a thickness of the intermediate insulating layer. ### Claim 3 (depends on 1) The method of manufacturing a semiconductor device of claim 1, wherein the separation structure includes a first insulating material, and wherein the intermediate insulating layer includes a second insulating material different from the first insulating material. ### Claim 4 (depends on 1) The method of manufacturing a semiconductor device of claim 1, further comprising: forming an insulating spacer on a sidewall of the preliminary opening, wherein a lower end of the insulating spacer is at a higher level than a lower surface of the intermediate insulating layer. ### Claim 5 (depends on 4) The method of manufacturing a semiconductor device of claim 4, further comprising: before forming the separation structure, removing the insulating spacer. ### Claim 6 (depends on 1) The method of manufacturing a semiconductor device of claim 1, further comprising: before forming the preliminary opening, forming a capping layer on the conductive structure, wherein the opening divides the capping layer into a first capping pattern and a second capping pattern. ### Claim 7 (depends on 1) The method of manufacturing a semiconductor device of claim 1, wherein each of the first conductive pattern and the second conductive pattern includes a first conductive layer and a second conductive layer on the first conductive layer, and wherein a thickness of the second conductive layer is greater than a thickness of the first conductive layer. ### Claim 8 (depends on 7) The method of manufacturing a semiconductor device of claim 7, wherein a distance between a lower surface of the first conductive layer of the first conductive pattern and a lower surface of the first conductive layer of the second conductive pattern is greater than a distance between an upper surface of the first conductive layer of the first conductive pattern and an upper surface of the first conductive layer of the second conductive pattern. ### Claim 9 (depends on 1) The method of manufacturing a semiconductor device of claim 1, wherein the maximum width of the intermediate portion is greater than a maximum width of the upper portion. ### Claim 10 (depends on 1) The method of manufacturing a semiconductor device of claim 1, wherein the intermediate portion includes: a first portion between the first conductive pattern and the lower insulating layer; a second portion between the second conductive pattern and the lower insulating layer; and a third portion between the first portion and the second portion. ### Claim 11 (depends on 1) The method of manufacturing a semiconductor device of claim 1, wherein the first conductive pattern and the second conductive pattern are spaced apart from each other by the separation structure, and wherein the first intermediate insulating pattern and the second intermediate insulating pattern are spaced apart from each other by the separation structure. ### Claim 12 A method of manufacturing a semiconductor device comprising: forming a lower insulating layer on a substrate; forming an intermediate insulating layer on the lower insulating layer; forming a conductive structure on the intermediate insulating layer; forming a preliminary opening penetrating through the conductive structure; forming an opening by partially etching the intermediate insulating layer and the lower insulating layer, after forming the preliminary opening; and forming a separation structure in the opening, wherein the opening divides the conductive structure into a first conductive pattern and a second conductive pattern, wherein the opening divides the intermediate insulating layer into a first intermediate insulating pattern and a second intermediate insulating pattern, wherein the separation structure includes: an intermediate portion between the first intermediate insulating pattern and the second intermediate insulating pattern; an upper portion upwardly extending from the intermediate portion and between the first conductive pattern and the second conductive pattern; and a lower portion downwardly extending from the intermediate portion and within the lower insulating layer, wherein the lower portion has a first lower side surface and a second lower side surface extending from the first lower side surface, and wherein the second lower side surface is bent from the first lower side surface. ### Claim 13 (depends on 12) The method of manufacturing a semiconductor device of claim 12, wherein the second lower side surface is at a higher level than the first lower side surface, and wherein a slope of the first lower side surface is steeper than a slope of the second lower side surface. ### Claim 14 (depends on 12) The method of manufacturing a semiconductor device of claim 12, wherein the upper portion has a first upper side surface and a second upper side surface extending from the first upper side surface, and wherein the second upper side surface is bent from the first upper side surface. ### Claim 15 (depends on 14) The method of manufacturing a semiconductor device of claim 14, wherein the second upper side surface is at a higher level than the first upper side surface, and wherein a slope of the second upper side surface is steeper than a slope of the first lower side surface. ### Claim 16 (depends on 12) The method of manufacturing a semiconductor device of claim 12, wherein a maximum width of an intermediate portion is greater than a maximum width of the lower portion. ### Claim 17 A method of manufacturing a semiconductor device comprising: forming a lower insulating layer on a substrate; forming an intermediate insulating layer on the lower insulating layer; forming a conductive structure on the intermediate insulating layer; forming a preliminary opening by etching at least a portion of the conductive structure; forming an insulating spacer on a sidewall of the preliminary opening; forming an opening by partially etching the intermediate insulating layer and the lower insulating layer, after forming the insulating spacer; and forming a separation structure in the opening, wherein the opening divides the conductive structure into a first conductive pattern and a second conductive pattern, and wherein the opening divides the intermediate insulating layer into a first intermediate insulating pattern and a second intermediate insulating pattern. ### Claim 18 (depends on 17) The method of manufacturing a semiconductor device of claim 17, wherein a maximum distance between the first intermediate insulating pattern and the second intermediate insulating pattern is greater than a maximum distance between the first conductive pattern and the second conductive pattern. ### Claim 19 (depends on 18) The method of manufacturing a semiconductor device of claim 18, wherein the maximum distance between the first intermediate insulating pattern and the second intermediate insulating pattern is greater than a maximum width of a portion of the opening within the lower insulating layer. ### Claim 20 (depends on 17) The method of manufacturing a semiconductor device of claim 17, further comprising: before forming the separation structure, removing the insulating spacer.