# US 12,113,108 B2 · Integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,108 B2 - Document ID: US12113108B2 - Status: Granted - Kind: B2 - Application number: 17/472,926 - Filed: 2021-09-13 - Published: 2022-08-04 - Granted: 2024-10-08 - Earliest claimed: 2021-02-04 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Dohee Kim; Gyeom Kim; Jinbum Kim; Haejun Yu; Kyungin Choi; Kihyun Hwang; Seunghun Lee - Web page: https://patentgrep.com/patent/US12113108B2 ## CPC - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation} - H10D 84/834: {comprising FinFETs} - H10W 20/076: {in via holes or trenches} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/0212: {using self-aligned silicidation} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/121: {oriented parallel to substrates} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 64/0112: {using conductive layers comprising silicides} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/251: {Source or drain electrodes for field-effect devices} - H10W 20/033: {in openings in dielectrics} - H10W 20/047: {by introducing additional elements therein} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region. ## Claims ### Claim 1 An integrated circuit device comprising: a fin-type active region extending along a first horizontal direction on a substrate; a plurality of gate structures each comprising a gate line extending along a second horizontal direction crossing the first horizontal direction on the fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between a first gate structure and a second gate structure, which are among the gate structures and are adjacent to each other, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact, wherein the source/drain contact comprises a lower contact portion facing the first gate structure and the second gate structure in the first horizontal direction and an upper contact portion that is integral to the lower contact portion, the upper contact portion comprises a horizontal extension, which extends on an upper corner of the first gate structure adjacent to the source/drain contact and overlaps at least a portion of the first gate structure in a vertical direction, wherein the insulation liner comprises a first local region that electrically separates the upper corner of the first gate structure and the horizontal extension of the source/drain contact, and a second local region that is farther from the substrate than the first local region, and wherein a thickness of the first local region is greater than that of the second local region. ### Claim 2 (depends on 1) The integrated circuit device of claim 1, wherein the first gate structure comprises a first gate line and a first insulation spacer between the first gate line and the source/drain contact, the first insulation spacer having a top portion defining a portion of the upper corner of the first gate structure, the second gate structure comprises a second gate line and a second insulation spacer between the second gate line and the source/drain contact, and at least a portion of the top portion of the first insulation spacer is closer to the substrate than a topmost surface of the second insulation spacer, and the first local region of the insulation liner is between the top portion and the source/drain contact. ### Claim 3 (depends on 1) The integrated circuit device of claim 1, wherein, in the first horizontal direction, a width of the upper contact portion of the source/drain contact is greater than a width of the lower contact portion. ### Claim 4 (depends on 1) The integrated circuit device of claim 1, wherein, in the first horizontal direction, a distance between the source/drain contact and the first gate structure is less than a distance between the source/drain contact and the second gate structure. ### Claim 5 (depends on 1) The integrated circuit device of claim 1, wherein the insulation liner further comprises a third local region that is closer to the substrate than the first local region, and the thickness of the first local region is greater than that of the third local region. ### Claim 6 (depends on 1) The integrated circuit device of claim 1, wherein the insulation liner comprises a first insulation liner including a portion in contact with the upper corner of the first gate structure and a second insulation liner stacked on the first insulation liner and including a portion in contact with the horizontal extension of the source/drain contact, the first insulation liner has a same thickness in the first local region and the second local region, and a thickness of the second insulation liner in the first local region is greater than a thickness of the second insulation liner in the second local region. ### Claim 7 (depends on 1) The integrated circuit device of claim 1, further comprising an inter-gate insulation layer between the second gate structure and the insulation liner, wherein the first gate structure is in contact with the insulation liner in the first horizontal direction, and the second gate structure is spaced apart from the insulation liner in the first horizontal direction with the inter-gate insulation layer therebetween. ### Claim 8 (depends on 1) The integrated circuit device of claim 1, wherein the source/drain contact is in a source/drain contact hole, and wherein the insulation liner comprises: a first insulation liner on an inner wall of the source/drain contact hole between the first gate structure and the second gate structure; and a second insulation liner between the first insulation liner and the source/drain contact and in contact with the source/drain contact, the first insulation liner has a uniform thickness within the source/drain contact hole, and the second insulation liner has a non-uniform thickness within the source/drain contact hole that is largest in the first local region. ### Claim 9 (depends on 6) The integrated circuit device of claim 6, wherein the first insulation liner comprises a first silicon nitride film, and the second insulation liner comprises a second silicon nitride film having a different density than the first silicon nitride film. ### Claim 10 (depends on 1) The integrated circuit device of claim 1, further comprising: a source/drain region on the fin-type active region between the first gate structure and the second gate structure; and a metal silicide layer between the source/drain region and the source/drain contact, the metal silicide layer having a bottom surface in contact with the source/drain region and a top surface in contact with the source/drain contact, wherein, in the first horizontal direction, a distance from the metal silicide layer to the first gate structure is less than a distance from the metal silicide layer to the second gate structure. ### Claim 11 An integrated circuit device comprising: a fin-type active region extending along a first horizontal direction on a substrate; a plurality of gate structures extending along a second horizontal direction crossing the first horizontal direction on the fin-type active regions; a source/drain region on the fin-type active region between a pair of gate structures among the gate structures, wherein the pair of gate structures are adjacent to each other; a source/drain contact that extends along a vertical direction on the source/drain region and has opposing sides in the first horizontal direction that are asymmetric; and an insulation liner on sidewalls of the source/drain contact, wherein the source/drain contact comprises a lower contact portion facing the pair of gate structures in the first horizontal direction and an upper contact portion that is integral to the lower contact portion, the upper contact portion comprises a horizontal extension, which extends on an upper corner of a first gate structure of the pair of gate structures and overlaps at least a portion of the first gate structure in the vertical direction, wherein the insulation liner comprises a first local region that electrically separates the upper corner of the first gate structure and the horizontal extension of the source/drain contact, and a second local region that is farther from the substrate than the first local region, and wherein a thickness of the first local region is greater than that of the second local region. ### Claim 12 (depends on 11) The integrated circuit device of claim 11, wherein opposing sides of the first gate structure are asymmetric in the first horizontal direction. ### Claim 13 (depends on 11) The integrated circuit device of claim 11, wherein the gate structures each comprise a gate line, an insulation capping line on a top surface of the gate line, and insulation spacers on sidewalls of the gate line and the insulation capping line, wherein the insulation spacer of the first gate structure has a top portion defining a portion of the upper corner, and wherein at least a portion of the top portion is closer to the substrate than a topmost surface of the first gate structure. ### Claim 14 (depends on 11) The integrated circuit device of claim 11, wherein the first gate structure comprises a first gate line and a second gate structure of the pair of gate structures comprises a second gate line, and wherein, in the first horizontal direction, a first distance between the source/drain contact and the first gate line is less than a second distance between the source/drain contact and the second gate line. ### Claim 15 (depends on 11) The integrated circuit device of claim 11, further comprising: a top insulation layer on top surfaces of the first gate structure and a second gate structure of the pair of gate structures, wherein the insulation liner and the source/drain contact penetrate through the top insulation layer in the vertical direction, and wherein the second local region of the insulation liner is between the top insulation layer and the source/drain contact. ### Claim 16 (depends on 11) The integrated circuit device of claim 11, wherein the insulation liner comprises a first insulation liner and a second insulation liner sequentially stacked on the first gate structure, the second insulation liner comprising a different material and/or density than the first insulation liner, wherein the first insulation liner has a same thickness in the first local region and the second local region, and wherein a thickness of the second insulation liner in the first local region is greater than a thickness of the second insulation liner in the second local region. ### Claim 17 (depends on 11) The integrated circuit device of claim 11, wherein the insulation liner further comprises a third local region between a sidewall of the first gate structure and the lower contact portion of the source/drain contact, and wherein the thickness of the first local region is greater than that of the third local region. ### Claim 18 (depends on 11) The integrated circuit device of claim 11, wherein the pair of gate structures comprises: the first gate structure comprising a first gate line extending along the second horizontal direction on the fin-type active region, a first insulation capping line on a top surface of the first gate line, and a first insulation spacer between the first gate line and the source/drain contact; and a second gate structure comprising a second gate line extending along the second horizontal direction on the fin-type active region, a second insulation capping line on a top surface of the second gate line, and a second insulation spacer between the second gate line and the source/drain contact, and, in the vertical direction, a height of a top surface of at least a portion of the first insulation spacer is less than a height of a topmost surface of the second insulation spacer relative to the substrate. ### Claim 19 An integrated circuit device comprising: a fin-type active region extending along a first horizontal direction on a substrate; a source/drain region on the fin-type active region, a pair of nanosheet stacks on a fin top surface of the fin-type active region and spaced apart from each other in the first horizontal direction with the source/drain region therebetween, a pair of gate structures comprising a pair of gate lines that surround the pair of nanosheet stacks on the fin-type active region and extend along a second horizontal direction crossing the first horizontal direction and a pair of outer insulation spacers on sidewalls of the pair of gate lines; a source/drain contact that extends along a vertical direction on the source/drain region and has opposing sides in the first horizontal direction that are asymmetric; and an insulation liner on sidewalls of the source/drain contact, wherein the source/drain contact comprises a lower contact portion between the pair of gate structures in the first horizontal direction and an upper contact portion extending from the lower contact portion, the upper contact portion comprises a horizontal extension, which extends on an upper corner of a first gate structure of the pair of gate structures and overlaps at least a portion of the first gate structure in the vertical direction, the insulation liner comprises a first local region between the upper corner of the first gate structure and the horizontal extension of the source/drain contact and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region. ### Claim 20 (depends on 19) The integrated circuit device of claim 19, wherein the insulation liner comprises a first insulation liner and a second insulation liner sequentially stacked on the first gate structure, the second insulation liner comprising a different material and/or density than the first insulation liner, wherein the first insulation liner is in contact with the first gate structure and has a same thickness in the first local region and the second local region, and wherein the second insulation liner is in contact with the source/drain contact and a thickness of the second insulation liner in the first local region is greater than a thickness of the second insulation liner in the second local region.