# US 12,113,107 B2 · Method for fabricating semiconductor device

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- Number: US 12,113,107 B2
- Document ID: US12113107B2
- Status: Granted
- Kind: B2
- Application number: 17/549,328
- Filed: 2021-12-13
- Published: 2022-11-03
- Granted: 2024-10-08
- Earliest claimed: 2021-04-28
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dae Won Kim; Tae Kyun Kim; Dong Goo Choi
- Web page: https://patentgrep.com/patent/US12113107B2

## CPC

- H10D 64/01: Manufacture or treatment
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for fabricating a semiconductor device includes: forming an insulating layer over a substrate including a cell region and a peripheral region; forming an opening in the insulating layer by selectively etching the insulating layer in the cell region; forming a plug conductive layer to fill the opening and cover the insulating film; etching the plug conductive layer and the insulating layer in the peripheral region by using a peri-open mask covering the cell region; trimming the peri-open mask to expose the plug conductive layer in a boundary region where the cell region and the peripheral region contact each other; etching the plug conductive layer in the boundary region by using the trimmed peri-open mask; forming a peri-gate conductive layer over the entire surface of the substrate; and etching the peri-gate conductive layer by using a cell open mask.

## Claims

### Claim 1

A method for fabricating a semiconductor device, the method comprising:
forming an insulating layer over a substrate, the substrate including a cell region and a peripheral region;
forming an opening by selectively etching the insulating layer over the substrate of the cell region;
forming a plug conductive layer to fill the opening and cover the insulating layer;
etching the plug conductive layer and the insulating layer over the substrate of the peripheral region by using a peri-open mask covering the cell region;
trimming the peri-open mask to expose the plug conductive layer over the substrate of a boundary region where the cell region and the peripheral region contact each other;
etching the plug conductive layer over the substrate of the boundary region by using the trimmed peri-open mask;
forming a peri-gate conductive layer over an entire surface of the substrate; and
etching the peri-gate conductive layer by using a cell open mask.

### Claim 2 (depends on 1)

The method of claim 1, before the forming of the peri-gate conductive layer, further including forming a barrier layer over the entire surface of the substrate.

### Claim 3 (depends on 2)

The method of claim 2, wherein the barrier layer has an etch selectivity with respect to the peri-gate conductive layer and the plug conductive layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein the barrier layer includes silicon oxide.

### Claim 5 (depends on 1)

The method of claim 1, wherein the peri-open mask includes a photoresist.

### Claim 6 (depends on 1)

The method of claim 1, wherein the etching of the peri-gate conductive layer using the cell open mask includes:
forming the cell open mask on the peri-gate conductive layer over the substrate of the peripheral region; and
etching the peri-gate conductive layer disposed over the substrate of the boundary region where the cell region and the peripheral region contact each other by using the trimmed cell open mask.

### Claim 7 (depends on 1)

The method of claim 1, wherein the cell open mask includes a photoresist.

### Claim 8 (depends on 1)

The method of claim 1, wherein the plug conductive layer includes a material having an etch selectivity with respect to the insulating layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the insulating layer includes silicon nitride.

### Claim 10 (depends on 1)

The method of claim 1, wherein the plug conductive layer includes polysilicon.

### Claim 11 (depends on 1)

The method of claim 1, wherein the peri-gate conductive layer includes a material having an etch selectivity with respect to the insulating layer.

### Claim 12 (depends on 1)

The method of claim 1, wherein the peri-gate conductive layer includes polysilicon.

### Claim 13 (depends on 1)

The method of claim 1, wherein the substrate of the cell region includes a buried gate structure.

### Claim 14 (depends on 13)

The method of claim 13, wherein the opening is disposed between neighboring buried gate structures.

### Claim 15 (depends on 13)

The method of claim 13, wherein a bottom surface of the opening is at a higher level than an upper surface of a gate electrode of the buried gate structure.

### Claim 16 (depends on 1)

The method of claim 1, further comprising:
after etching the peri-gate conductive layer by using the cell open mask,
sequentially forming a bitline conductive layer and a bitline hardmask layer over the entire surface of the substrate; and
forming a bitline structure over the substrate of the cell region and a peri-gate structure over the substrate of the peripheral region by using a pattern mask.

### Claim 17 (depends on 16)

The method of claim 16, wherein the pattern mask includes a first pattern mask and a second pattern mask having different line widths.