# US 12,113,105 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,105 B2 - Document ID: US12113105B2 - Status: Granted - Kind: B2 - Application number: 17/720,711 - Filed: 2022-04-14 - Published: 2023-10-19 - Granted: 2024-10-08 - Earliest claimed: 2022-04-14 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Nao Nagata - Web page: https://patentgrep.com/patent/US12113105B2 ## CPC - H10D 62/141: {Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/145: {Emitter regions of IGBTs} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes first and second active cell regions and an inactive cell region between the first and second active cell regions, wherein each of the first and second active cell regions comprises: a trench gate; a first trench emitter; a first hole barrier layer of a first conductivity type formed between the trench gate and the first trench emitter; a base layer of a second conductivity type formed on upper portion of the first hole barrier layer; an emitter layer of the first conductivity type formed on upper portion of the base layer; a latch-up prevention layer of the second conductivity type formed on upper portion of the first hole barrier layer, wherein the inactive cell region comprises: a second trench emitter; a first floating layer of the second conductivity type formed between the trench gate of the first active cell region and the second trench emitter. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface; and a drift layer of a first conductivity type formed on the semiconductor substrate, wherein the semiconductor substrate has first and second active cell regions, and an inactive cell region between the first and second active cell regions, wherein each of the first and second active cell regions comprises: a trench gate formed on the first surface side; a first trench emitter formed adjacent to the trench gate on the first surface side; a first hole barrier layer of the first conductivity type formed on upper portion of the drift layer and between the trench gate and the first trench emitter; a base layer of a second conductivity type opposite to the first conductivity type formed on upper portion of the first hole barrier layer and in contact with the trench gate; an emitter layer of the first conductivity type formed on upper portion of the base layer and in contact with the trench gate; and a latch-up prevention layer of the second conductivity type formed on upper portion of the first hole barrier layer and in contact with the first trench emitter, wherein the inactive cell region comprises: a second trench emitter formed adjacent to the trench gate of the first active region on the first surface side; and a first floating layer of the second conductivity type formed between the trench gate of the first active cell region and the second trench emitter. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first floating layer is also formed between the second trench emitter and the first trench emitter of the second active cell region. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the inactive cell region further includes third and fourth trench emitters formed on the first surface side, wherein the trench gate and the first and second trench emitters extend in a first direction in a plan view, wherein the third and fourth trench emitters extend in a second direction perpendicular to the first direction in a plan view, and wherein the second trench emitter and the first trench emitter of the second active cell region is connected to the third and fourth trench emitters so as to be square in a plan view. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the inactive cell region has first and second inactive cell regions adjacent to each other in the first direction in a plan view, and wherein a second hole barrier layer of the first conductivity type is formed between the fourth trench emitter of the first inactive cell region and the third trench emitter of the second inactive cell region. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein a parasitic P-channel MOSFET is formed by the latch-up prevention layer, the first hole barrier layer and the first floating layer, and wherein a parasitic P-channel MOSFET is formed by the latch-up prevention layer, the second hole barrier layer and the first floating layer. ### Claim 6 (depends on 3) The semiconductor device according to claim 3, wherein the inactive cell region has first and second inactive cell regions adjacent to each other in the first direction in a plan view, and wherein the first trench emitter of the first inactive cell region is connected to the first trench emitter of the second inactive cell region so as to have a shape extending continuously in the first direction. ### Claim 7 (depends on 3) The semiconductor device according to claim 3, wherein the inactive cell region further comprises a fifth emitter trench formed on the first surface side and between the first and second trench emitters, and wherein the fifth trench emitter extends in the first direction in a plan view and is connected to the third and fourth trench emitters. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the inactive cell region further comprising: a second floating layer of the second conductivity type formed between the second trench emitter and the fifth trench emitter, and a third floating layer of the second conductivity type formed between the first trench emitter and the fifth trench emitter. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein a floating layer of the first conductivity type is formed on lower portion of the second floating layer. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein a parasitic P-channel MOSFET is formed by the latch-up prevention layer, the first hole barrier layer and the third floating layer. ### Claim 11 (depends on 2) The semiconductor device according to claim 2, wherein a depth of the second trench emitter from the first surface is shallower than a depth of the first floating layer from the first surface. ### Claim 12 (depends on 2) The semiconductor device according to claim 2, wherein a parasitic P-channel MOSFET is formed by the latch-up prevention layer, the first hole barrier layer and the first floating layer. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein a distance between the second trench emitter and the trench gate of the first active cell region is shorter than a distance between the second trench emitter and the first trench emitter of the second active cell region.