# US 12,113,103 B2 · Charge-balance power device, and process for manufacturing the charge-balance power device

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- Number: US 12,113,103 B2
- Document ID: US12113103B2
- Status: Granted
- Kind: B2
- Application number: 18/062,524
- Filed: 2022-12-06
- Published: 2023-04-06
- Granted: 2024-10-08
- Earliest claimed: 2019-07-31
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMICROELECTRONICS S.r.l.
- Inventors: Antonello Santangelo; Giuseppe Longo; Lucio Renna
- Web page: https://patentgrep.com/patent/US12113103B2

## CPC

- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/051: {Forming charge compensation regions, e.g. superjunctions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.

## Claims

### Claim 1

A device, comprising:
a first doped layer having a first surface opposite to a second surface;
a gate region in the first doped layer, the gate region including:
a gate dielectric having a first end and a second end, the first end extending past the first surface of the first doped layer, the second end being adjacent to the second surface of the first doped layer;
a gate conductor in the gate dielectric, the gate conductor is closer to the first end than the second end, the gate conductor partially extending past the first surface of the first doped layer, and the gate conductor being completely surrounded by the gate dielectric; and
a second doped layer fully within the first doped layer, the second doped layer being on sides of the gate dielectric and being on the second end of the gate dielectric, the second doped layer terminates at ends along the sides of the gate dielectric and terminates at the ends within the first doped layer, and the ends of the second doped layer are fully covered by the first doped layer and are in direct contact with the first doped layer; and
a source region on at least one of the sides of the gate dielectric and having a third surface facing away from the first doped layer, and
wherein the gate dielectric and the gate conductor extending past the source region and extending past the third surface.

### Claim 2 (depends on 1)

The device of claim 1 wherein the second doped layer is between the gate dielectric and the first doped layer.

### Claim 3 (depends on 2)

The device of claim 2, comprising a conductive layer on the first doped layer and on the gate dielectric that extends past the first surface of the first doped layer.

### Claim 4 (depends on 3)

The device of claim 3, comprising a plurality of body regions in the first doped layer, the gate dielectric being between adjacent ones of the plurality of body regions.

### Claim 5 (depends on 4)

The device of claim 4, wherein the source region is on the plurality of body regions, and the conductive layer is on the source.

### Claim 6 (depends on 5)

The device of claim 5 wherein the plurality of body regions has a first conductivity type and the second doped layer has the first conductivity type.

### Claim 7 (depends on 6)

The device of claim 6 wherein the source has a second conductivity type that is different from the first conductivity type.

### Claim 8 (depends on 7)

The device of claim 7 wherein the first doped layer has the second conductivity type.

### Claim 9

A device, comprising:
a substrate of a first conductivity type;
a first doped layer on the substrate, the first doped layer is of the first conductivity type;
a body region in the first doped layer, the body region is of a second conductivity type, the body region has a first surface;
a conductive layer on the surface of the body region, the conductive layer covers the surface of the body region;
a source region between the body region and the conductive layer, the source region including a second surface covered by the conductive layer;
a gate region having a first end and a second end, the first end being in the substrate, the second end in the conductive layer, the gate region including:
a gate dielectric that extends from the first end to the second end; and
a gate conductor that is completely within and surrounded by the gate dielectric, that is closer to the second end than the first end, and that extends past the first surface of the body region and extends past the second surface of the source region.

### Claim 10 (depends on 9)

The device of claim 9 wherein the source region is of the first conductivity type.

### Claim 11 (depends on 10)

The device of claim 10, comprising a second doped layer on sides of the gate dielectric, the second doped layer being between the gate dielectric and the first doped layer.

### Claim 12 (depends on 11)

The device of claim 11 wherein the second doped layer is the second conductivity type.

### Claim 13 (depends on 12)

The device of claim 12 wherein the second doped layer is spaced from the substrate by a portion of the first doped layer.

### Claim 14 (depends on 9)

The device of claim 9 further comprising a second doped layer on sides of the gate dielectric, the second doped layer being between the gate dielectric layer and the first doped layer, the second doped layer terminating at ends along the sides of the gate dielectric and terminates at the ends within the first doped layer, and the ends of the second doped layer are fully covered by the first doped layer and are in direct contact with the first doped layer.

### Claim 15

A device, comprising:
a first doped layer of a first conductivity type;
a second doped layer on the first doped layer, the second doped layer of the first conductivity type;
a body region in the second doped layer, the body region having a second conductivity type, and the body region includes a first surface;
a source region on the body region, the source region including a second surface;
a third doped layer completely within the second doped layer, the third doped layer of the second conductivity type;
a conductive layer on the first surface of the body region and on the second surface of the source region;
a first and second columnar gate dielectric in the second doped layer, the third doped layer being on sides of the first and second columnar gate dielectrics, the first and second columnar gate dielectrics having a first end in the conductive layer and a second end in the second doped layer, and the second end being opposite to the first end; and
a first and second gate conductor are in and completely surrounded by the first and second columnar gate dielectrics, respectively, the first and second gate conductors being closer to the conductive layer than the first doped layer, and the first and second gate conductors extend past the first surface of the body region and the second surface of the source region to be within the conductive layer, and wherein
the third doped layer covers the second ends of the first and second columnar gate dielectrics, the third doped layer terminates at ends before extending along the sides of the first and second columnar gate dielectrics to the first and second gate conductors, respectively, the ends of the third doped layer are fully covered by the second doped layer and are in direct contact with the second doped layer.

### Claim 16 (depends on 15)

The device of claim 15 wherein the third doped layer is spaced from the first doped layer.

### Claim 17 (depends on 15)

The device of claim 15 wherein the second ends of the first and second columnar gate dielectrics are in the first doped layer.

### Claim 18 (depends on 15)

The device of claim 15 wherein the third doped layer is spaced apart from the conductive layer.

### Claim 19 (depends on 15)

The device of claim 15 wherein the source region is between the body region and the conductive layer.

### Claim 20 (depends on 19)

The device of claim 19 wherein the first ends of the first and second columnar gate dielectrics extend past the source and into the conductive layer.

### Claim 21 (depends on 20)

The device of claim 20 wherein the gate conductor extends past the source and into the conductive layer.