# US 12,113,102 B2 · Semiconductor device with guard ring isolating power device

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- Number: US 12,113,102 B2
- Document ID: US12113102B2
- Status: Granted
- Kind: B2
- Application number: 17/575,166
- Filed: 2022-01-13
- Published: 2022-12-15
- Granted: 2024-10-08
- Earliest claimed: 2021-06-14
- Assignees: SK keyfoundry Inc.
- Applicants: SK keyfoundry Inc.
- Inventors: Kwangil Kim; Taehoon Lee; Hyunchul Kim; Insu Jung; Kyungbae Lee
- Web page: https://patentgrep.com/patent/US12113102B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/529: {Electrodes for IGFETs contacting substrate regions, e.g. for grounding or preventing parasitic effects}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A power device and a guard ring structure surrounding the power device are provided. The power device includes: a buried layer of a first conductivity type and a buried layer of a second conductivity type disposed within a substrate; a body region of the first conductivity type and a drift region of the second conductivity type disposed on the buried layer of the first conductivity type; and a gate electrode, a source electrode, and a drain electrode disposed on the body region of the first conductivity type and the drift region of the second conductivity type. The guard ring structure includes: a first guard ring of the second conductivity type adjacent to the power device; a second guard ring of the first conductivity type adjacent to the first guard ring; and a third guard ring of the second conductivity type adjacent to the second guard ring.

## Claims

### Claim 1

A semiconductor device, comprising:
a power device; and
a guard ring structure which is disposed to surround the power device,
wherein the power device comprises:
a buried layer of a first conductivity type, and a buried layer of a second conductivity type, each layer disposed within a substrate;
a body region of the first conductivity type and a drift region of the second conductivity type which are disposed on the buried layer of the first conductivity type;
a gate electrode, a source electrode, and a drain electrode which are disposed on the body region of the first conductivity type and the drift region of the second conductivity type, and
a second conductivity type deep well region disposed between the buried layer of the second conductivity type and the guard ring structure,
wherein the guard ring structure is disposed on the second conductivity type deep well region,
wherein the guard ring structure comprises:
a first guard ring of the second conductivity type disposed adjacent to the power device;
a second guard ring of the first conductivity type disposed adjacent to the first guard ring; and
a third guard ring of the second conductivity type disposed adjacent to the second guard ring, and
wherein the buried layer of the second conductivity type is disposed to extend to the guard ring structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first conductivity type is different from the second conductivity type.

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein the first guard ring is configured to surround the power device,
wherein the second guard ring is configured to surround the first guard ring, and wherein the third guard ring is configured to surround the second guard ring.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein each of the first guard ring and the third guard ring comprises:
a second conductivity type well; and
a second conductivity type impurity layer which is disposed within the second conductivity type well, and
wherein the second guard ring comprises:
a first conductivity type well; and
a first conductivity type impurity layer which is disposed within the first conductivity type well.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the guard ring structure further comprises:
a fourth guard ring of the first conductivity type disposed adjacent to the third guard ring; and
a fifth guard ring of the second conductivity type disposed adjacent to the fourth guard ring.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first guard ring, the second guard ring, and the third guard ring are configured to receive a same bias voltage.

### Claim 7

A semiconductor device, comprising:
a power device, which is disposed on a substrate, and comprising a gate electrode, a source electrode, and a drain electrode; and
a guard ring structure which is configured to surround the power device,
wherein the guard ring structure comprises:
an N-type first guard ring disposed adjacent to the power device;
a P-type second guard ring disposed adjacent to the N-type first guard ring; and
an N-type third guard ring disposed adjacent to the P-type second guard ring, and
wherein the N-type first guard ring, the P-type second guard ring, and the N-type third guard ring are configured to receive a same first bias,
wherein the power device comprises an N-type buried layer disposed in the substrate and an N-type deep well region configured to be in contact with lower portions of the first guard ring, the second guard ring, and the third guard ring, and
wherein the N-type deep well region is disposed between the guard ring structure and the N-type buried layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the guard ring structure further comprises:
a P-type fourth guard ring disposed adjacent to the N-type third guard ring; and
an N-type fifth guard ring disposed adjacent to the P-type fourth guard ring.

### Claim 9 (depends on 7)

The semiconductor device of claim 7,
wherein each of the N-type first guard ring and the N-type third guard ring comprises:
an N-type well; and
an N-type impurity layer which is disposed within the N-type well, and
wherein the P-type second guard ring comprises:
a P-type well; and
a P-type impurity layer which is disposed within the P-type well.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein the power device further comprises:
a P-type buried layer disposed on the N-type buried layer;
a P-type body region and an N-type drift region disposed on the P-type buried layer;
an N-type source region disposed in the P-type body region; and
an N-type drain region disposed in the N-type drift region.

### Claim 11 (depends on 7)

The semiconductor device of claim 7,
wherein the power device is disposed in a power block,
wherein the power block comprises a power supply voltage PVCC and a ground voltage PGND,
wherein the first bias applied to the first guard ring, the second guard ring, and the third guard ring is connected to the power supply voltage PVCC,
wherein the drain electrode of the power device is connected to the power supply voltage PVCC, so that the drain electrode and the guard ring structure are connected to the same power supply voltage PVCC,
and wherein a second bias is applied to the substrate, and the second bias is connected to the ground voltage PGND.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the N-type deep well region and the P-type buried layer are disposed adjacent to each other.

### Claim 13

A semiconductor device, comprising:
a power device;
a circuit block region;
a guard ring structure, configured to surround the power device,
a P-type well region, configured to surround the guard ring structure, and disposed between the circuit block region and the guard ring structure,
a first buried layer of a first conductivity type disposed in a substrate; and
a deep N-type well region disposed in the substrate between the guard ring structure and the first buried layer of a first conductivity type,
wherein the guard ring structure comprises:
an N-type first guard ring;
a P-type second guard ring, and
an N-type third guard ring.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, further comprising:
a second buried layer of a second conductivity type disposed in the substrate.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein the N-type first guard ring, the P-type second guard ring, and the N-type third guard ring are configured to receive a same bias voltage.