# US 12,113,100 B2 · Semiconductor structure and method for manufacturing semiconductor structure

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- Number: US 12,113,100 B2
- Document ID: US12113100B2
- Status: Granted
- Kind: B2
- Application number: 17/509,152
- Filed: 2021-10-25
- Published: 2022-07-28
- Granted: 2024-10-08
- Earliest claimed: 2021-01-28
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Hongmin Wu; Yu-Sheng Ting
- Web page: https://patentgrep.com/patent/US12113100B2

## CPC

- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching}
- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 1/714: {having horizontal extensions}
- H10D 1/716: {having vertical extensions}
- H10B 12/033: {the capacitor extending over the transistor}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Provided are a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a substrate in which a capacitor structure is formed, and the capacitor structure includes a lower electrode plate, a dielectric layer, an upper electrode plate and a protective layer. The lower electrode plate is located on the substrate. The dielectric layer covers a surface of the lower electrode plate. The upper electrode plate covers the dielectric layer. The protective layer is formed on a surface of the upper electrode plate parallel to the substrate.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate in which a capacitor structure is formed, the capacitor structure comprising:
a lower electrode plate located on the substrate;
a dielectric layer covering a surface of the lower electrode plate;
an upper electrode plate covering the dielectric layer; and
a protective layer formed on a surface, parallel to the substrate, of the upper electrode plate, wherein the protective layer has a doping element, and the doping element reacts with the upper electrode plate to generate the protective layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the protective layer comprises metal silicide.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the upper electrode plate comprises polysilicon, and the doping element comprises at least one of nickel, cobalt, titanium, copper, molybdenum, tantalum or tungsten.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the upper electrode plate comprises an upper electrode and an upper electrode filling layer, the upper electrode covers a surface of the dielectric layer, and the upper electrode filling layer covers the upper electrode.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the upper electrode filling layer is polysilicon.

### Claim 6 (depends on 4)

The semiconductor structure of claim 4, wherein an outer side surface of the upper electrode filling layer has a concave-convex side structure, and the semiconductor structure further comprises: an oxide layer covering surfaces of the upper electrode filling layer and the protective layer.

### Claim 7 (depends on 4)

The semiconductor structure of claim 4, further comprising:
a plug located on the substrate and spaced apart from the upper electrode filling layer.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the capacitor structure is a pillar-shaped capacitor structure, a cup-shaped capacitor structure or a trench-type capacitor structure.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the substrate comprises a contact pad in contact with the lower electrode plate directly.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a capacitance contact plug connected with the upper electrode plate.

### Claim 11

A method for manufacturing a semiconductor structure, comprising:
providing a substrate, and forming a capacitor structure in the substrate, wherein forming the capacitor structure comprises:
forming a lower electrode plate on the substrate;
forming a dielectric layer on a surface of the lower electrode plate;
forming an upper electrode plate on a surface of the dielectric layer; and
forming a protective layer on a surface, parallel to the substrate, of the upper electrode plate, wherein a doping element reacts with the upper electrode plate to generate the protective layer.

### Claim 12 (depends on 11)

The method for manufacturing the semiconductor structure of claim 11, wherein generating the protective layer comprises:
performing ion doping on an outer surface of the upper electrode plate and then performing annealing on the doped outer surface to generate the protective layer.

### Claim 13 (depends on 11)

The method for manufacturing the semiconductor structure of claim 11, wherein generating the protective layer comprises:
forming a metal material layer on the upper electrode plate; and
enabling the metal material layer to react with the upper electrode plate to generate the protective layer.

### Claim 14 (depends on 13)

The method for manufacturing the semiconductor structure of claim 13, wherein forming the capacitor structure further comprises: before the metal material layer is formed,
forming a spin-coated carbon layer on a surface of the upper electrode plate, and exposing the surface of the upper electrode plate parallel to the substrate,
wherein the metal material layer is formed on the spin-coated carbon layer and covers an upper portion of the upper electrode plate.

### Claim 15 (depends on 14)

The method for manufacturing the semiconductor structure of claim 14, wherein after the protective layer is formed, the spin-coated carbon layer is removed, and the protective layer is used as a mask for etching downwards to remove the upper electrode plate and the dielectric layer located outside a side wall of the protective layer.

### Claim 16 (depends on 11)

The method for manufacturing the semiconductor structure of claim 11, wherein forming the capacitor structure further comprises:
removing the upper electrode plate located outside a side wall of the protective layer downwards along the side wall of the protective layer.

### Claim 17 (depends on 16)

The method for manufacturing the semiconductor structure of claim 16, further comprising:
forming a capacitance contact plug on the substrate, the capacitance contact plug being connected with the upper electrode plate.

### Claim 18 (depends on 11)

The method for manufacturing the semiconductor structure of claim 11, further comprising:
forming a plug on the substrate, the plug being spaced apart from the upper electrode plate.