# US 12,113,099 B2 · Deep trench capacitor including stress-relief voids and methods of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,099 B2 - Document ID: US12113099B2 - Status: Granted - Kind: B2 - Application number: 18/359,023 - Filed: 2023-07-26 - Published: 2023-11-16 - Granted: 2024-10-08 - Earliest claimed: 2021-08-27 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Limited - Inventors: Fu-Chiang Kuo - Web page: https://patentgrep.com/patent/US12113099B2 ## CPC - H10D 1/692: {Electrodes} - H01G 4/012: Form of non-self-supporting electrodes - H01G 4/08: Inorganic dielectrics - H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} - H01G 4/35: Feed-through capacitors or anti-noise capacitors - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors} - H10D 1/716: {having vertical extensions} - H10P 14/44: Physical vapour deposition [PVD] - H10W 20/48: Insulating materials thereof - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor. ## Claims ### Claim 1 A method of forming a semiconductor structure, the method comprising: forming a deep trench in a substrate; forming a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers over the substrate, wherein the layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench; and depositing a dielectric fill material layer comprising a dielectric fill material in the cavity and over the substrate, wherein the dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity such that all surfaces of the void within the dielectric fill material layer are surfaces of the dielectric fill material layer. ### Claim 2 (depends on 1) The method of claim 1, wherein the dielectric fill material layer is deposited by a non-conformal deposition process that deposits the dielectric fill material at a higher deposition rate at an opening of the deep trench than at a bottom portion of the deep trench. ### Claim 3 (depends on 1) The method of claim 1, wherein the at least three metallic electrode layers and the at least two node dielectric layers are deposited by a respective conformal deposition process. ### Claim 4 (depends on 1) The method of claim 1, wherein the at least three metallic electrode layers comprise a conductive metallic nitride, an elemental metal, or an intermetallic alloy. ### Claim 5 (depends on 1) The method of claim 1, wherein the at least two node dielectric layers comprise a dielectric metal oxide or silicon nitride. ### Claim 6 (depends on 1) The method of claim 1, wherein the dielectric fill material layer comprises undoped silicate glass, a doped silicate glass, silicon oxynitride, a silicon oxide carbide, or organosilicate glass. ### Claim 7 (depends on 1) The method of claim 1, further comprising depositing a conformal dielectric liner directly on the layer stack, wherein the conformal dielectric liner comprises undoped silicate glass or a doped silicate glass. ### Claim 8 (depends on 7) The method of claim 7, wherein the dielectric fill material layer is deposited directly on the conformal dielectric liner and comprises at least one element that is not present within the conformal dielectric liner. ### Claim 9 (depends on 1) The method of claim 1, further comprising: depositing a dielectric liner on a top surface of the substrate and on sidewalls of the deep trench, wherein the layer stack is formed on the dielectric liner; forming a contact-level dielectric layer over the dielectric fill material layer; and forming contact via structures through contact-level dielectric layer on a respective one of the at least three metallic electrode layers. ### Claim 10 (depends on 1) The method of claim 1, further comprising: forming a first semiconductor die including the substrate, the layer stack, and the dielectric fill material layer; and bonding the first semiconductor die to a second semiconductor die through bonding pads or solder material portions. ### Claim 11 A method of forming a semiconductor structure, the method comprising: forming at least one deep trench in an upper portion of a substrate; forming a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers in the at least one deep trench, wherein the layer stack continuously extending over the top surface of the substrate and into each of the at least one deep trench; and forming a dielectric fill material layer comprising a dielectric fill material and including a horizontally-extending portion that overlies a topmost surface of the layer stack and at least one vertically-extending portion that extends downward from the horizontally-extending portion into a center region of a respective one of the at least one deep trench, wherein the at least one vertically-extending portion comprises a void that is free of any solid phase material such that all surfaces of the void within the at least one vertically-extending portion are surfaces of the dielectric fill material layer. ### Claim 12 (depends on 11) The method of claim 11, wherein each of the at least one vertically-extending portion of the dielectric fill material layer is laterally surrounded by vertically-extending portions of the at least three metallic electrode layers and the at least two node dielectric layers. ### Claim 13 (depends on 11) The method of claim 11, wherein Young's modulus of the dielectric fill material layer is less than Young's modulus of a material of the at least three metallic electrode layers, and is less than Young's modulus of a material of the at least two node dielectric layers. ### Claim 14 (depends on 11) The method of claim 11, wherein: the at least three metallic electrode layers comprise a conductive metallic nitride, an elemental metal, or an intermetallic alloy; and the at least two node dielectric layers comprise a dielectric metal oxide or silicon nitride. ### Claim 15 (depends on 11) The method of claim 11, wherein the dielectric fill material layer comprises undoped silicate glass, a doped silicate glass, silicon oxynitride, a silicon oxide carbide, or organosilicate glass. ### Claim 16 (depends on 11) The method of claim 11, wherein the void has a height-to-width ratio that is greater than 5. ### Claim 17 A method of forming a semiconductor structure, comprising: forming at least one deep trench extending downward from a top surface of the semiconductor substrate; forming a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers and continuously extending over the top surface of the semiconductor substrate and into each of the at least one deep trench; and forming a dielectric fill material layer including a void that is free of any solid phase material on the layer stack such that all surfaces of the void within the dielectric fill material layer are surfaces of the dielectric fill material layer. ### Claim 18 (depends on 17) The method of claim 17, wherein the void is formed within a vertically-extending portion of the dielectric fill material layer that is located within one of the at least one deep trench. ### Claim 19 (depends on 17) The method of claim 17, further comprising: patterning horizontally-extending portions of the layer stack and the dielectric fill material layer; forming a contact-level dielectric layer over the layer stack and the dielectric fill material layer; and forming contact via structures through the contact-level dielectric layer on a respective one of the at least three metallic electrode layers, wherein one of the contact via structures vertically extends through, and contacts, a horizontally-extending portion of the dielectric fill material layer. ### Claim 20 (depends on 17) The method of claim 17, wherein Young's modulus of the dielectric fill material layer is less than Young's modulus of a material of the at least three metallic electrode layers, and is less than Young's modulus of a material of the at least two node dielectric layers.