# US 12,113,086 B2 · Apparatus and methods for sensing long wavelength light

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- Number: US 12,113,086 B2
- Document ID: US12113086B2
- Status: Granted
- Kind: B2
- Application number: 18/232,323
- Filed: 2023-08-09
- Published: 2023-12-14
- Granted: 2024-10-08
- Earliest claimed: 2020-08-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yun-Wei Cheng; Chun-Hao Chou; Kuo-Cheng Lee; Ying-Hao Chen
- Web page: https://patentgrep.com/patent/US12113086B2

## CPC

- H10F 39/807: {Pixel isolation structures}
- H10F 71/139: {using temporary substrates}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 71/121: {The active layers comprising only Group IV materials}
- H10F 77/122: comprising only Group IV materials
- H10F 77/306: {for devices having potential barriers}
- H10F 39/024: {of coatings or optical elements}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.

## Claims

### Claim 1

A semiconductor device, comprising:
a device layer having a plurality of devices formed therein;
a semiconductor layer on the device layer, wherein:
the semiconductor layer comprises a plurality of isolation regions and a plurality of pixel regions, and
the plurality of pixel regions comprises a second semiconductor material that is different from the first semiconductor material; and
an insulation layer on the semiconductor layer,
wherein the insulation layer comprises silicon oxide to serve as a passivation layer for the semiconductor layer,
wherein the plurality of devices are located entirely below a respective one of the plurality of isolation regions and positioned entirely outside the plurality of pixel regions,
wherein the semiconductor layer has a first surface and a second surface opposite to the first surface that is adjacent to the device layer, and
wherein the second surface has a non-flat and periodic surface structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second semiconductor material has a band gap smaller than that of the first semiconductor material.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the plurality of pixel regions are evenly distributed in the semiconductor layer based on a predetermined design; and
each of the plurality of isolation regions is located between two adjacent pixel regions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor layer comprises a light sensing sublayer including a plurality of light sensing regions, wherein each of the plurality of pixel regions comprises a corresponding one of the plurality of light sensing regions.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein:
each of the plurality of light sensing regions comprises the second semiconductor material and a doping material; and
doping concentrations of the plurality of light sensing regions are different from each other based on a predetermined design.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein:
the semiconductor layer has a first thickness between 2 micrometers and 10 micrometers; and
each of the plurality of light sensing regions in the light sensing sublayer has a second thickness that is equal to or smaller than the first thickness.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein:
each of the plurality of isolation regions comprises a trench isolation and an implanted well surrounding the trench isolation, and
the trench isolation comprises a dielectric material.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein:
the implanted well comprises a first semiconductor material, and
the trench isolation is one of: a shallow trench isolation, or a deep trench isolation.

### Claim 9

An image sensor, comprising:
a device layer comprising at least one device; and
a semiconductor layer on the device layer, wherein the semiconductor layer comprises a silicon region and a plurality of light sensing regions surrounded by the silicon region, wherein
each of the plurality of light sensing regions comprises a same semiconductor material and a same doping material,
doping concentrations of the plurality of light sensing regions are different from each other based on a predetermined design,
wherein the at least one device is located below the silicon region without contacting the same semiconductor material in the plurality of light sensing regions,
wherein the semiconductor layer has a first surface and a second surface opposite to the first surface that is adjacent to the device layer, and
wherein the second surface has a non-flat and periodic surface structure.

### Claim 10 (depends on 9)

The image sensor of claim 9, wherein the same semiconductor material is germanium.

### Claim 11 (depends on 9)

The image sensor of claim 9, wherein the plurality of devices comprises a plurality of transistors.

### Claim 12 (depends on 9)

The image sensor of claim 9, wherein the plurality of devices comprises a plurality of logic devices.

### Claim 13 (depends on 9)

The image sensor of claim 9, wherein:
the silicon region is thicker than the plurality of light sensing regions.

### Claim 14

A method for forming an image sensor, comprising:
forming a patterned structure on a first surface of an insulation layer;
growing a first semiconductor material on the insulation layer to form a semiconductor layer on and in contact with the first surface of the insulation layer;
etching the semiconductor layer to determine a plurality of etched regions in the semiconductor layer;
growing a second semiconductor material in the plurality of etched regions to form a plurality of light sensing regions in the semiconductor layer; and
forming a dielectric layer over the semiconductor layer,
wherein the patterned structure of the first surface increases a quantum efficiency of the image sensor compared to a flat surface structure.

### Claim 15 (depends on 14)

The method of claim 14, wherein wherein the semiconductor layer has a first surface and a second surface opposite to the first surface, wherein the second surface has a non-flat and periodic surface structure.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
doping each of the plurality of light sensing regions such that a doping concentration varies from one light sensing region to another based on a predetermined design.

### Claim 17 (depends on 14)

The method of claim 14, further comprising:
determining, in the semiconductor layer, a plurality of isolation regions each of which is between two adjacent light sensing regions; and
doping each of the plurality of isolation regions to generate an implanted well in the isolation region.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming a device layer including a plurality of devices on the semiconductor layer, wherein:
the dielectric layer is formed on the device layer; and
each of the plurality of devices is located on one of the plurality of isolation regions.

### Claim 19 (depends on 18)

The method of claim 18, further comprising removing the semiconductor substrate on the insulation layer, wherein at least part of the insulation layer is kept to serve as a passivation layer for the semiconductor layer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
forming a deep trench in each of the plurality of isolation regions, wherein the at least part of the insulation layer has a top surface and a bottom surface that is opposite to the top surface and is in contact with the semiconductor layer, and the deep trench extends from the top surface of the insulation layer into a corresponding one of the plurality of isolation regions; and
forming an isolation structure in the deep trench in each of the plurality of isolation regions.