# US 12,113,079 B2 · Image sensor with shallow trench edge doping > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,079 B2 - Document ID: US12113079B2 - Status: Granted - Kind: B2 - Application number: 18/342,877 - Filed: 2023-06-28 - Published: 2023-11-09 - Granted: 2024-10-08 - Earliest claimed: 2017-10-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yueh-Chuan Lee; Chia-Chan Chen - Web page: https://patentgrep.com/patent/US12113079B2 ## CPC - H10F 39/8037: {the integrated elements comprising a transistor} - H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers} - H10F 39/014: {of CMOS image sensors} - H10F 39/8033: {Photosensitive area} - H10F 39/807: {Pixel isolation structures} - H10P 14/3438: {Doping during depositing} - H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices - H10W 10/01: {Manufacture or treatment} - H10W 15/00: Highly-doped buried regions of integrated devices - H10W 15/01: {Manufacture or treatment} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure relates to an integrated chip. The integrated chip includes a gate structure on a substrate. A doped region is within the substrate. One or more dielectric materials are within a recess formed by one or more surfaces of the substrate. The doped region is laterally between the gate structure and the recess. A doped epitaxial material is within the recess and between the one or more dielectric materials and the doped region. The doped epitaxial material is asymmetric about a vertical line that extends through a lateral center of the doped epitaxial material. ## Claims ### Claim 1 An integrated chip, comprising: a gate structure on a substrate; a doped region within the substrate; one or more dielectric materials within a recess formed by one or more surfaces of the substrate, the doped region laterally between the gate structure and the recess; and a doped epitaxial material within the recess and between the one or more dielectric materials and the doped region, wherein the doped epitaxial material is asymmetric about a vertical line that extends through a lateral center of the doped epitaxial material. ### Claim 2 (depends on 1) The integrated chip of claim 1, wherein the doped epitaxial material has an outermost sidewall that is within the recess and that is laterally separated by non-zero distances from opposing sidewalls of the substrate that form the recess. ### Claim 3 (depends on 1) The integrated chip of claim 1, wherein the one or more dielectric materials comprise a first sidewall contacting an outermost sidewall of the doped epitaxial material, the outermost sidewall of the doped epitaxial material vertically extending to a larger height than the first sidewall. ### Claim 4 (depends on 1) The integrated chip of claim 1, wherein an entirety of the doped epitaxial material is laterally outside of the one or more dielectric materials. ### Claim 5 (depends on 1) The integrated chip of claim 1, further comprising: a dielectric protection layer arranged on a top surface of the one or more dielectric materials within the recess, the dielectric protection layer having a top surface that is below a top surface of the doped epitaxial material. ### Claim 6 (depends on 1) The integrated chip of claim 1, wherein the doped epitaxial material continuously lines the substrate within the recess and directly above a top of the doped region. ### Claim 7 (depends on 1) The integrated chip of claim 1, further comprising: a color filter disposed on the substrate; and a micro-lens disposed on the color filter, wherein the micro-lens is configured to focus incident radiation towards a photodiode comprising the doped region. ### Claim 8 (depends on 7) The integrated chip of claim 7, wherein the gate structure is arranged along a first side of the substrate and the color filter and the micro-lens are arranged along a second side of the substrate opposing the first side of the substrate. ### Claim 9 (depends on 1) The integrated chip of claim 1, wherein the doped epitaxial material protrudes outward from within the recess to above the recess. ### Claim 10 An integrated chip, comprising: a gate structure disposed on a semiconductor substrate; a doped region disposed within the semiconductor substrate; one or more dielectric materials arranged directly between sidewalls of the semiconductor substrate; and a doped material arranged directly between the sidewalls of the semiconductor substrate, wherein the doped material has a first outermost sidewall facing the gate structure and a second outermost sidewall facing the one or more dielectric materials, the first outermost sidewall having a first length and the second outermost sidewall having a second length that is different than the first length. ### Claim 11 (depends on 10) The integrated chip of claim 10, wherein the doped material has a topmost surface that faces away from the semiconductor substrate and that continuously extends between the first outermost sidewall and the second outermost sidewall of the doped material. ### Claim 12 (depends on 10) The integrated chip of claim 10, wherein the second length is larger than the first length. ### Claim 13 (depends on 10) The integrated chip of claim 10, wherein a horizontally extending surface of the semiconductor substrate, which is between the sidewalls of the semiconductor substrate, extends in opposing directions for non-zero distances past the second outermost sidewall of the doped material. ### Claim 14 (depends on 10) The integrated chip of claim 10, wherein the doped material has a bottommost surface that is laterally separated from the first outermost sidewall of the doped material by a non-zero distance. ### Claim 15 (depends on 10) The integrated chip of claim 10, further comprising: a well region disposed within the semiconductor substrate between the doped region and the doped material, the well region having a first doping type; and wherein the doped material has the first doping type and laterally contacts the well region. ### Claim 16 (depends on 15) The integrated chip of claim 15, wherein the well region has a first doping concentration and the doped material has a second doping concentration that is higher than the first doping concentration. ### Claim 17 (depends on 16) The integrated chip of claim 16, wherein the first doping concentration is in a range of between approximately 1×1015 atoms/cm3 and approximately 1×1017 atoms/cm3 and the second doping concentration is greater than approximately 1×1017 atoms/cm3. ### Claim 18 An integrated chip, comprising: a gate structure arranged over a substrate between a photodiode region and a floating diffusion region, the photodiode region and the floating diffusion region being disposed within the substrate; one or more sidewall spacers arranged along opposing sides of the gate structure; a first well region arranged within the substrate along a side of the photodiode region, wherein the photodiode region is laterally between the first well region and the gate structure; one or more dielectric materials disposed within a trench formed by sidewalls of the substrate, the trench separated from the photodiode region by the first well region; and a doped material disposed within the trench and extending from within the trench to directly above the photodiode region and along an outermost sidewall of the one or more sidewall spacers, wherein the doped material has an outermost sidewall that is arranged within the trench and that faces the one or more dielectric materials within the trench, the outermost sidewall of the doped material being laterally separated from the sidewalls of the substrate by non-zero distances. ### Claim 19 (depends on 18) The integrated chip of claim 18, wherein the outermost sidewall of the doped material extends vertically above a top of the one or more dielectric materials. ### Claim 20 (depends on 18) The integrated chip of claim 18, further comprising: a second well region laterally surrounding the floating diffusion region and having a same doping type as the first well region, wherein the first well region has a larger doping concentration than the second well region.