# US 12,113,073 B2 · Array substrate, manufacturing method thereof and display panel

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- Number: US 12,113,073 B2
- Document ID: US12113073B2
- Status: Granted
- Kind: B2
- Application number: 17/618,488
- Filed: 2021-11-25
- Published: 2024-01-11
- Granted: 2024-10-08
- Earliest claimed: 2021-11-12
- Assignees: Huizhou China Star Optoelectronics Display Co., Ltd.; Tcl China Star Optoelectronics Technology Co., Ltd.
- Applicants: Huizhou China Star Optoelectronics Display Co., Ltd.; Tcl China Star Optoelectronics Technology Co., Ltd.
- Inventors: Xu Huang
- Web page: https://patentgrep.com/patent/US12113073B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided are an array substrate, a manufacturing method thereof and a display panel; the array substrate includes a thin film transistors disposed on a base substrate, and a conductive channel of the thin film transistor is formed on a contact surface of the first semiconductor layer and the second semiconductor layer. It can avoid the interface defect state caused by the material difference when the existing conductive channel is formed on the side of the semiconductor layer close to the insulating layer, thereby solving the problem of poor lighting stability in the existing oxide semiconductor thin film transistor.

## Claims

### Claim 1

An array substrate, comprising a base substrate and a thin film transistor disposed on the base substrate, and the thin film transistor comprises a first gate, a first semiconductor layer, a second semiconductor layer, a second gate, a source electrode and a drain electrode which are sequentially disposed on the base substrate, wherein a conductive channel of the thin film transistor is formed on a contact surface of the first semiconductor layer and the second semiconductor layer; and wherein a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein materials of the first semiconductor layer and the second semiconductor layer comprise indium gallium zinc oxide.

### Claim 3 (depends on 2)

The array substrate according to claim 2, wherein a content of gallium in the first semiconductor layer is less than a content of gallium in the second semiconductor layer.

### Claim 4 (depends on 1)

The array substrate according to claim 1, wherein both the first gate and the second gate are connected to a negative voltage.

### Claim 5 (depends on 4)

The array substrate according to claim 4, further comprising:
a first gate insulating layer, covering the first gate and the base substrate, and the first semiconductor layer is disposed on the first insulating layer and the second semiconductor layer is disposed on the first semiconductor layer, and an orthographic projection of the second semiconductor layer on the base substrate is within an orthographic projection of the first semiconductor layer on the base substrate;
a second gate insulating layer, covering the second semiconductor layer, and the second gate is disposed on the second insulating layer, and the second gate is disposed corresponding to the conductive channel;
an interlayer insulating layer, covering the second gate and the first gate insulating layer, and the source electrode and the drain electrode are disposed on the interlayer insulating layer, and a plurality of first via holes are disposed in the interlayer insulating layer;
wherein the first semiconductor layers located on both sides of the conductive channel form a source region and a drain region of the thin film transistor, and the source electrode and the drain electrode are respectively connected to the source region and the drain region through the corresponding first via holes.

### Claim 6 (depends on 5)

The array substrate according to claim 5, wherein the thin film transistor further comprises a bridge electrode, and the second gate is electrically connected to the first gate through the bridge electrode.

### Claim 7 (depends on 6)

The array substrate according to claim 6, wherein the bridge electrode and the source electrode are disposed in a same layer, and the interlayer insulating layer is further disposed with a second via hole and a third via hole, and the bridge electrode is connected to the second gate through the second via hole, and is connected to the first gate through the third via hole.

### Claim 8 (depends on 5)

The array substrate according to claim 5, wherein the orthographic projection of the first semiconductor layer on the base substrate is within an orthographic projection of the first gate on the base substrate.

### Claim 9 (depends on 5)

The array substrate according to claim 5, wherein a length of the second semiconductor layer is smaller than a length of the first semiconductor layer.

### Claim 10

A display panel, comprising an array substrate, and the array substrate comprises a base substrate and a thin film transistor disposed on the base substrate, and the thin film transistor comprises a first gate, a first semiconductor layer, a second semiconductor layer, a second gate, a source electrode and a drain electrode which are sequentially disposed on the base substrate, wherein a conductive channel of the thin film transistor is formed on a contact surface of the first semiconductor layer and the second semiconductor layer; and wherein a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.

### Claim 11 (depends on 10)

The display panel according to claim 10, wherein materials of the first semiconductor layer and the second semiconductor layer comprise indium gallium zinc oxide.

### Claim 12 (depends on 11)

The display panel according to claim 11, wherein a content of gallium in the first semiconductor layer is less than a content of gallium in the second semiconductor layer.

### Claim 13 (depends on 10)

The display panel according to claim 10, wherein both the first gate and the second gate are connected to a negative voltage.

### Claim 14 (depends on 10)

The display panel according to claim 10, wherein a length of the second semiconductor layer is smaller than a length of the first semiconductor layer.

### Claim 15

A manufacturing method of an array substrate, comprising a step of providing a base substrate, and a step of manufacturing a thin film transistor on the base substrate, wherein the step of manufacturing the thin film transistor comprises:
preparing a first gate on the base substrate;
preparing a first gate insulating layer on the first gate and the base substrate, and preparing a first semiconductor layer on the first gate insulating layer;
preparing a second semiconductor layer on the first semiconductor layer;
preparing a second gate insulating layer on the second semiconductor layer and preparing a second gate on the second gate insulating layer, and employing the second gate as a shield to etch the second gate insulating layer and the second semiconductor layer to expose part of the first semiconductor layer, wherein a conductive channel of the thin film transistor is formed on a contact surface of the first semiconductor layer and the second semiconductor layer, and the first semiconductor layers located on both sides of the conductive channel form a source region and a drain region of the thin film transistor;
preparing an interlayer insulating layer on the second gate and the first gate insulating layer, and patterning the interlayer insulating layer to form a plurality of first via holes and preparing a source electrode and a drain electrode on the interlayer insulating layer, and the source electrode and the drain electrode are respectively connected to the source region and the drain region through the corresponding first via holes.

### Claim 16 (depends on 15)

The manufacturing method of the array substrate according to claim 15, wherein the step of preparing the first semiconductor layer on the first gate insulating layer comprises:
implementing a magnetron sputtering method to sputter an indium gallium zinc oxide target material with a gallium content of a first preset value on the first gate insulating layer to form the first semiconductor layer in an atmosphere of a first preset O2/Ar ratio.

### Claim 17 (depends on 16)

The manufacturing method of the array substrate according to claim 16, wherein the step of preparing the second semiconductor layer on the first semiconductor layer comprises:
implementing a magnetron sputtering method to sputter an indium gallium zinc oxide target material with a gallium content of a second preset value on the first semiconductor layer to form the second semiconductor layer in an atmosphere of a second preset O2/Ar ratio, wherein a value of the second preset O2/Ar ratio is greater than a value of the first preset O2/Ar ratio and the second preset value is greater than the first preset value, so that a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.

### Claim 18 (depends on 15)

The manufacturing method of the array substrate according to claim 15, wherein the manufacturing method further comprises:
the step of patterning the interlayer insulating layer further forms a second via hole and a third via hole, and while forming the source electrode and the drain electrode on the interlayer insulating layer, a bridge electrode is further formed, and the bridge electrode is connected to the second gate through the second via hole, and is connected to the first gate through the third via hole, so that both the first gate and the second gate are connected to a negative voltage.