# US 12,113,071 B2 · Multi-function substrate

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- Number: US 12,113,071 B2
- Document ID: US12113071B2
- Status: Granted
- Kind: B2
- Application number: 17/869,827
- Filed: 2022-07-21
- Published: 2022-11-03
- Granted: 2024-10-08
- Earliest claimed: 2020-12-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Eugene I-Chun Chen; Kuan-Liang Liu; Szu-Yu Wang; Chia-Shiung Tsai; Ru-Liang Lee; Chih-Ping Chao; Alexander Kalnitsky
- Web page: https://patentgrep.com/patent/US12113071B2

## CPC

- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10P 90/1906: {Preparing SOI wafers}
- H10P 90/1914: {using bonding}
- H10P 90/1918: {including charge trapping layers, e.g. polycrystalline materials}
- H10P 90/192: {irregularly shaped charge trapping layers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/36: {characterised by treatments done before the formation of the materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

## Claims

### Claim 1

An integrated chip, comprising:
a polysilicon layer arranged on an upper surface of a base substrate, wherein the polysilicon layer comprises grain sizes that increase from a lower surface of the polysilicon layer to an upper surface of the polysilicon layer;
a dielectric layer arranged over the polysilicon layer;
an active semiconductor layer arranged over the dielectric layer; and
a semiconductor material arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

### Claim 2 (depends on 1)

The integrated chip of claim 1, wherein the base substrate comprises:
a semiconductor body; and
an epitaxial layer arranged on the semiconductor body, wherein the semiconductor material is disposed on the epitaxial layer.

### Claim 3 (depends on 2)

The integrated chip of claim 2, wherein the epitaxial layer continuously extends from directly below the semiconductor material to directly below the polysilicon layer.

### Claim 4 (depends on 1)

The integrated chip of claim 1, further comprising:
a gap fill structure arranged along sidewalls of the semiconductor material, the active semiconductor layer, and the dielectric layer, wherein the gap fill structure laterally separates the sidewall of the semiconductor material from the sidewalls of the dielectric layer and the active semiconductor layer.

### Claim 5 (depends on 1)

The integrated chip of claim 1, further comprising:
an isolation structure comprising one or more dielectric materials arranged between a sidewall of the semiconductor material and sidewalls of the active semiconductor layer and the dielectric layer.

### Claim 6 (depends on 1)

The integrated chip of claim 1, wherein the polysilicon layer has a gradient doping concentration that decreases from the lower surface of the polysilicon layer to within the polysilicon layer.

### Claim 7 (depends on 1)

The integrated chip of claim 1, further comprising:
an inter-level dielectric (ILD) structure continuously extending from directly over the active semiconductor layer to directly over the semiconductor material; and
a plurality of interconnects disposed within the ILD structure.

### Claim 8

An integrated chip, comprising:
a semiconductor body having a first region and a second region, wherein one or more defects are disposed along an upper surface of the semiconductor body within the second region;
an epitaxial layer disposed over the semiconductor body, wherein the epitaxial layer covers the one or more defects;
a polysilicon layer arranged over the semiconductor body and within the first region;
a dielectric layer arranged over the polysilicon layer;
an active semiconductor layer arranged over the dielectric layer; and
a semiconductor material arranged over the epitaxial layer and within the second region, wherein the semiconductor material extends to above top surfaces of the polysilicon layer and the dielectric layer.

### Claim 9 (depends on 8)

The integrated chip of claim 8, wherein the polysilicon layer is arranged directly between sidewalls of the epitaxial layer.

### Claim 10 (depends on 8)

The integrated chip of claim 8, wherein the one or more defects comprise one or more crystal originated particle (COP) defects.

### Claim 11 (depends on 8)

The integrated chip of claim 8, wherein the polysilicon layer extends completely through the epitaxial layer to contact the semiconductor body.

### Claim 12 (depends on 8)

The integrated chip of claim 8, wherein the polysilicon layer comprises a sidewall arranged along a sidewall of the epitaxial layer and a bottommost surface that is separated from the semiconductor body by the epitaxial layer.

### Claim 13 (depends on 8)

The integrated chip of claim 8, wherein the epitaxial layer continuously extends from below an uppermost surface of the polysilicon layer to above the uppermost surface of the polysilicon layer.

### Claim 14 (depends on 8)

The integrated chip of claim 8, wherein the polysilicon layer continuously extends from along a sidewall of the epitaxial layer to above an uppermost surface of the epitaxial layer.

### Claim 15 (depends on 8)

The integrated chip of claim 8, further comprising:
a gap fill structure laterally arranged between an outermost sidewall of the semiconductor material and outermost sidewalls of both the dielectric layer and the active semiconductor layer that face the outermost sidewall of the semiconductor material.

### Claim 16

An integrated chip, comprising:
a polysilicon layer arranged on a base substrate;
a dielectric arranged over the polysilicon layer;
an active semiconductor layer arranged over the dielectric;
a semiconductor material arranged vertically over the base substrate and laterally beside the active semiconductor layer;
a gap fill structure arranged laterally between the active semiconductor layer and the semiconductor material, wherein the gap fill structure has a bottom surface facing the base substrate and a top surface facing away from the base substrate, the top surface being wider than the bottom surface; and
wherein the gap fill structure has opposing outermost sidewalls that extend below a top of the dielectric.

### Claim 17 (depends on 16)

The integrated chip of claim 16, wherein the base substrate comprises an epitaxial layer arranged over a semiconductor body, the polysilicon layer being over the epitaxial layer and the gap fill structure being above a top surface of the epitaxial layer.

### Claim 18 (depends on 17)

The integrated chip of claim 17, wherein a bottom of the polysilicon layer is below the top surface of the epitaxial layer.

### Claim 19 (depends on 16)

The integrated chip of claim 16, wherein the polysilicon layer includes grain sizes that increase as a distance over the base substrate increases.

### Claim 20 (depends on 16)

The integrated chip of claim 16, wherein a part of the gap fill structure that is below the top of the dielectric is directly over a part of the semiconductor material in a cross-sectional view.