# US 12,113,070 B2 · Transistor integration on a silicon-on-insulator substrate

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- Number: US 12,113,070 B2
- Document ID: US12113070B2
- Status: Granted
- Kind: B2
- Application number: 17/830,830
- Filed: 2022-06-02
- Published: 2023-12-07
- Granted: 2024-10-08
- Earliest claimed: 2022-06-02
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GlobalFoundries U.S. Inc.
- Inventors: Peter Baars; Viorel Ontalus; Ketankumar H. Tailor; Michael Zier; Crystal R. Kenney; Judson Holt
- Web page: https://patentgrep.com/patent/US12113070B2

## CPC

- H10D 62/137: {Collector regions of BJTs}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 86/01: Manufacture or treatment
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

## Claims

### Claim 1

A structure comprising:
a semiconductor substrate including a trench;
a first semiconductor layer including a portion adjacent to the trench;
a dielectric layer between the first semiconductor layer and the semiconductor substrate, the dielectric layer having an interface with the first semiconductor layer;
a second semiconductor layer in the trench, the second semiconductor layer including a first portion that is recessed relative to the interface;
a first shallow trench isolation region in the second semiconductor layer; and
a vertical heterojunction bipolar transistor including a collector in the first portion of the second semiconductor layer and a base layer, the base layer including a first portion that overlaps with the first shallow trench isolation region.

### Claim 2 (depends on 1)

The structure of claim 1 wherein the collector is positioned below the interface, and further comprising:
a field-effect transistor including a gate electrode on the first semiconductor layer, the gate electrode positioned above the interface.

### Claim 3 (depends on 2)

The structure of claim 2 wherein the first semiconductor layer has a thickness in a range of about 1 nanometers to about 20 nanometers.

### Claim 4 (depends on 1)

The structure of claim 1 wherein the vertical heterojunction bipolar transistor includes a sub-collector in the semiconductor substrate, and the sub-collector is positioned in a vertical direction beneath the trench.

### Claim 5 (depends on 4)

The structure of claim 4 wherein the trench has a width, and the sub-collector comprises a well that extends in a lateral direction in the semiconductor substrate over an entirety of the width of the trench.

### Claim 6 (depends on 4)

The structure of claim 4 wherein the vertical heterojunction bipolar transistor includes a doped region in the first portion of the second semiconductor layer, the doped region is coupled by the sub-collector with the collector, and further comprising:
a contact extending in the vertical direction to the doped region.

### Claim 7 (depends on 4)

The structure of claim 4 wherein the base layer includes a second portion that overlaps with the collector, the vertical heterojunction bipolar transistor includes an emitter on the base layer, and the base layer is fully positioned in the vertical direction below the interface.

### Claim 8 (depends on 1)

The structure of claim 1 wherein the base layer includes a second portion that overlaps with the collector, and the base layer is fully positioned in a vertical direction below the interface.

### Claim 9 (depends on 1)

The structure of claim 1 wherein the first shallow trench isolation region penetrates partially through the second semiconductor layer.

### Claim 10 (depends on 8)

The structure of claim 8 wherein the vertical heterojunction bipolar transistor includes an emitter on the base layer, and the emitter extends from the base layer above the interface.

### Claim 11 (depends on 1)

The structure of claim 1 further comprising:
a second shallow trench isolation region in the second semiconductor layer, the second shallow trench isolation region including a first portion adjacent to the portion of the second semiconductor layer and a second portion, the first portion recessed relative to the interface, and the second portion projecting above the first portion to define a step.

### Claim 12 (depends on 11)

The structure of claim 11 wherein the second semiconductor layer includes a second portion that is not recessed relative to the interface, the trench includes a sidewall, and the second portion of the second semiconductor layer is positioned in a lateral direction between the first portion of the second semiconductor layer and the sidewall of the trench.

### Claim 13 (depends on 1)

The structure of claim 1 further comprising:
a deep trench isolation region penetrating through the first semiconductor layer and the dielectric layer into the semiconductor substrate.

### Claim 14 (depends on 13)

The structure of claim 13 wherein the vertical heterojunction bipolar transistor includes a sub-collector in the semiconductor substrate, the sub-collector is positioned in a vertical direction below the trench, the first shallow trench isolation region is positioned in the vertical direction fully above the sub-collector, and the deep trench isolation region penetrates to a depth below the sub-collector.

### Claim 15 (depends on 1)

The structure of claim 1 wherein the trench includes a sidewall, and further comprising:
a dielectric collar positioned between the first semiconductor layer and the sidewall of the trench.

### Claim 16 (depends on 1)

The structure of claim 1 wherein the base layer comprises silicon-germanium, and the second semiconductor layer comprises single-crystal silicon.

### Claim 17 (depends on 1)

The structure of claim 1 wherein the vertical heterojunction bipolar transistor includes an emitter, and the base layer is disposed in a vertical direction between the emitter and the collector in the second semiconductor layer.

### Claim 18 (depends on 1)

The structure of claim 1 wherein the first shallow trench isolation region comprises a dielectric material.

### Claim 19 (depends on 11)

The structure of claim 11 wherein the first shallow trench isolation region and the second shallow trench isolation region penetrate partially through the second semiconductor layer.

### Claim 20

A method comprising:
forming a trench in a semiconductor substrate, wherein a first semiconductor layer includes a portion adjacent to the trench, a dielectric layer is positioned between the first semiconductor layer and the semiconductor substrate, and the dielectric layer has an interface with the first semiconductor layer;
forming a second semiconductor layer in the trench, wherein the second semiconductor layer includes a portion that is recessed relative to the interface;
forming a shallow trench isolation region in the second semiconductor layer; and
forming a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer and a base layer, wherein the base layer includes a portion that overlaps with the shallow trench isolation region.