# US 12,113,069 B2 · Thermal extraction of single layer transfer integrated circuits

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- Number: US 12,113,069 B2
- Document ID: US12113069B2
- Status: Granted
- Kind: B2
- Application number: 17/901,189
- Filed: 2022-09-01
- Published: 2023-03-09
- Granted: 2024-10-08
- Earliest claimed: 2018-07-19
- Assignees: Murata Manufacturing Co., Ltd.
- Applicants: Murata Manufacturing Co., Ltd.
- Inventors: Abhijeet Paul; Richard James Dowling; Hiroshi Yamada; Alain Duvallet; Ronald Eugene Reedy
- Web page: https://patentgrep.com/patent/US12113069B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/01: Manufacture or treatment
- H10W 20/42: Vias, e.g. via plugs
- H10W 40/037: {Assembling together parts thereof}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10D 30/674: {characterised by the active materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

## Claims

### Claim 1

A method of making a thermal conduction structure for an integrated circuit transistor device, including:
(a) fabricating at least one dummy gate electrically isolated from the transistor device by a gate oxide and in thermal contact with the transistor device;
(b) fabricating at least one thermal path electrically isolated from the transistor device and in thermal contact with at least one dummy gate, the at least one thermal path configured to convey heat from the transistor device to a heat sink.

### Claim 2 (depends on 1)

The method of claim 1, wherein the dummy gate comprises polysilicon.

### Claim 3 (depends on 1)

The method of claim 1, further including fabricating at least one thermal path at least in part by fabricating at least one metallization layer overlaying at least a portion of at least one dummy gate and extending laterally from the transistor device.

### Claim 4 (depends on 1)

The method of claim 1, wherein the integrated circuit transistor device is made using a silicon-on-insulator (SOI) process.