# US 12,113,068 B2 · Fabrication of gate-all-around integrated circuit structures having additive metal gates > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,068 B2 - Document ID: US12113068B2 - Status: Granted - Kind: B2 - Application number: 17/031,832 - Filed: 2020-09-24 - Published: 2022-03-24 - Granted: 2024-10-08 - Earliest claimed: 2020-09-24 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Dan S. Lavric; Dax M. Crum; Omair Saadat; Oleg Golonzka; Tahir Ghani - Web page: https://patentgrep.com/patent/US12113068B2 ## CPC - H10D 84/853: {comprising FinFETs} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/01: Manufacture or treatment - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants} - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 62/364: {of IGFETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer. ## Claims ### Claim 1 An integrated circuit structure, comprising: a first vertical arrangement of horizontal nanowires; a second vertical arrangement of horizontal nanowires; a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the P-type conductive layer is laterally between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, the second portion of the P-type conductive layer having a first sidewall and a second sidewall laterally opposite to the first sidewall, wherein the first sidewall and the second sidewall are vertical sidewalls of a same continuous portion of the P-type conductive layer, and wherein the second portion of the P-type conductive layer has an uppermost surface above an uppermost surface of one or more of the nanowires of the first vertical arrangement of horizontal nanowires or the second vertical arrangement of horizontal nanowires; and a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the first sidewall and the second sidewall of the second portion of the P-type conductive layer. ### Claim 2 (depends on 1) The integrated circuit structure of claim 1, wherein the first portion of the P-type conductive layer does not include erosion features. ### Claim 3 (depends on 1) The integrated circuit structure of claim 1, further comprising: a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires. ### Claim 4 (depends on 3) The integrated circuit structure of claim 3, further comprising: a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and a second pair of conductive contacts on the second pair of epitaxial source or drain structures. ### Claim 5 (depends on 3) The integrated circuit structure of claim 3, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures. ### Claim 6 (depends on 3) The integrated circuit structure of claim 3, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of discrete epitaxial source or drain structures. ### Claim 7 An integrated circuit structure, comprising: a first vertical arrangement of horizontal nanowires; a second vertical arrangement of horizontal nanowires; a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the N-type conductive layer is laterally between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, the second portion of the N-type conductive layer having a first sidewall and a second sidewall laterally opposite to the first sidewall, wherein the first sidewall and the second sidewall are vertical sidewalls of a same continuous portion of the N-type conductive layer, and wherein the second portion of the N-type conductive layer has an uppermost surface above an uppermost surface of one or more of the nanowires of the first vertical arrangement of horizontal nanowires or the second vertical arrangement of horizontal nanowires; and a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the first sidewall and the second sidewall of the second portion of the N-type conductive layer. ### Claim 8 (depends on 7) The integrated circuit structure of claim 7, wherein the first portion of the P-type conductive layer does not include erosion features. ### Claim 9 (depends on 7) The integrated circuit structure of claim 7, further comprising: a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires. ### Claim 10 (depends on 9) The integrated circuit structure of claim 9, further comprising: a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and a second pair of conductive contacts on the second pair of epitaxial source or drain structures. ### Claim 11 (depends on 9) The integrated circuit structure of claim 9, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures. ### Claim 12 (depends on 9) The integrated circuit structure of claim 9, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of discrete epitaxial source or drain structures. ### Claim 13 A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a first vertical arrangement of horizontal nanowires; a second vertical arrangement of horizontal nanowires; a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the P-type conductive layer is laterally between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, the second portion of the P-type conductive layer having a first sidewall and a second sidewall laterally opposite to the first sidewall, wherein the first sidewall and the second sidewall are vertical sidewalls of a same continuous portion of the P-type conductive layer, and wherein the second portion of the P-type conductive layer has an uppermost surface above an uppermost surface of one or more of the nanowires of the first vertical arrangement of horizontal nanowires or the second vertical arrangement of horizontal nanowires; and a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the first sidewall and the second sidewall of the second portion of the P-type conductive layer. ### Claim 14 (depends on 13) The computing device of claim 13, further comprising: a memory coupled to the board. ### Claim 15 (depends on 13) The computing device of claim 13, further comprising: a communication chip coupled to the board. ### Claim 16 (depends on 13) The computing device of claim 13, wherein the component is a packaged integrated circuit die. ### Claim 17 (depends on 13) The computing device of claim 13, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. ### Claim 18 A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a first vertical arrangement of horizontal nanowires; a second vertical arrangement of horizontal nanowires; a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the N-type conductive layer is laterally between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, the second portion of the N-type conductive layer having a first sidewall and a second sidewall laterally opposite to the first sidewall, wherein the first sidewall and the second sidewall are vertical sidewalls of a same continuous portion of the N-type conductive layer, and wherein the second portion of the N-type conductive layer has an uppermost surface above an uppermost surface of one or more of the nanowires of the first vertical arrangement of horizontal nanowires or the second vertical arrangement of horizontal nanowires; and a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the first sidewall and the second sidewall of the second portion of the N-type conductive layer. ### Claim 19 (depends on 18) The computing device of claim 18, further comprising: a memory coupled to the board. ### Claim 20 (depends on 18) The computing device of claim 18, further comprising: a communication chip coupled to the board. ### Claim 21 (depends on 18) The computing device of claim 18, wherein the component is a packaged integrated circuit die. ### Claim 22 (depends on 18) The computing device of claim 18, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.