# US 12,113,063 B2 · Semiconductor device including vertical routing structure and method for manufacturing the same

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- Number: US 12,113,063 B2
- Document ID: US12113063B2
- Status: Granted
- Kind: B2
- Application number: 18/103,210
- Filed: 2023-01-30
- Published: 2023-06-08
- Granted: 2024-10-08
- Earliest claimed: 2017-11-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wei-Chih Wen; Han-Ting Tsai; Chung-Te Lin
- Web page: https://patentgrep.com/patent/US12113063B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/01: {Manufacture or treatment}
- H10N 50/01: Manufacture or treatment
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

## Claims

### Claim 1

A semiconductor device, the device comprising:
a transistor on a substrate, the transistor having a source region and a drain region;
a first to an N-th wiring layers, each of which includes:
an interlayer dielectric layer;
a source-side via disposed in the interlayer dielectric layer and over the source region and a drain-side via disposed in the interlayer dielectric layer and over the drain region; and
a source-side wiring in contact with the source-side via and a drain-side wiring in contact with the drain-side via; and
a controlled device disposed over an uppermost drain-side via,
wherein:
the source-side vias in the first to the N-th wiring layers overlap with each other in plan view,
the drain-side vias in the first to the N-th wiring layers overlap with each other in plan view,
two of the source-side wirings in the first to the N-th wiring layers extend in different directions from each other in plan view.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the source-side wirings in (2M−1)-th wiring layers extend in a first direction, and the source-side wirings in 2M-th wiring layers extend in a second direction different from the first direction.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, where N is at least four.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the two of the source side wirings comprise rectangular structures in plan view.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the controlled device includes one of a magnetic random access memory (MRAM) cell, a phase change random access memory (PCRAM) cell or a resistance change random access memory (RRAM) cell.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the controlled device overlaps the drain-side vias in plan view.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the source-side vias have a same area in a plan view.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the drain-side wirings in the first to the N-th wiring layers have a same area in plan view.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the drain-side vias have a same area in a plan view.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the drain-side vias have a smaller area than the drain-side wirings in a plan view.

### Claim 11

A semiconductor device, the device comprising:
a transistor on a substrate, the transistor having a source region and a drain region;
a first to an N-th wiring layers, each of which includes:
an interlayer dielectric layer;
a source-side via disposed in the interlayer dielectric layer and over the source region and a drain-side via disposed in the interlayer dielectric layer and over the drain region; and
a source-side wiring in contact with the source-side via and a drain-side wiring in contact with the drain-side via; and
a controlled device disposed over an uppermost drain-side via,
wherein:
the source-side vias in the first to the N-th wiring layers overlap with each other in plan view,
the drain-side vias in the first to the N-th wiring layers overlap with each other in plan view, and
at least one of the source-side wirings in the first to the N-th wiring layers and at least one of the drain-side wirings in the first to the N-th wiring layers extend in a first direction in plan view.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein at least one of the source-side wirings in the first to the N-th wiring layers extends in a second direction crossing the first direction in plan view.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the at least one of the source-side wirings and the at least one of the drain-side wirings comprise rectangular structures in plan view.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the controlled device includes a memory cell.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the controlled device overlaps the drain-side vias in plan view.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, further comprising an electronic device coupled to the at least one of the drain-side wirings.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, further comprising an electronic device coupled to the at least one of the source-side wirings.

### Claim 18

A semiconductor device, the device comprising:
a transistor on a substrate, the transistor having a source region and a drain region;
a first to an N-th wiring layers, each of which includes:
an interlayer dielectric layer;
a source-side via disposed in the interlayer dielectric layer and over the source region and a drain-side via disposed in the interlayer dielectric layer and over the drain region; and
a source-side wiring in contact with the source-side via and a drain-side wiring in contact with the drain-side via; and
a controlled device disposed over an uppermost drain-side via,
wherein:
the source-side vias in the first to the N-th wiring layers overlap with each other in plan view,
the drain-side vias in the first to the N-th wiring layers overlap with each other in plan view, and
at least one of the source-side wirings in the first to the N-th wiring layers includes an L-shape wiring in plan view.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the at least one of the source-side wirings comprises rectangular segments forming the L-shape wiring in plan view.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the controlled device includes a memory cell.