# US 12,113,062 B2 · Fringe capacitor, integrated circuit and manufacturing process for the fringe capacitor

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- Number: US 12,113,062 B2
- Document ID: US12113062B2
- Status: Granted
- Kind: B2
- Application number: 17/137,784
- Filed: 2020-12-30
- Published: 2022-06-30
- Granted: 2024-10-08
- Earliest claimed: 2020-12-30
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Naveen Tipirneni; Maik Peter Kaufmann; Michael Lueders; Jungwoo Joh
- Web page: https://patentgrep.com/patent/US12113062B2

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H02M 1/0009: {Devices or circuits for detecting current in a converter}
- H02M 1/0058: {by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero (using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826)}
- H02M 3/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections}
- H10D 1/692: {Electrodes}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/472: {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 84/01: Manufacture or treatment
- H10D 84/05: using Group III-V technology
- H10W 20/496: {Capacitor integral with wiring layers}
- H02M 1/0029: {Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate}
- H02M 1/32: Means for protecting converters other than automatic disconnection
- H02M 1/44: Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
- H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators
- H02M 7/06: using discharge tubes without control electrode or semiconductor devices without control electrode
- H03K 3/0377: {Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

## Claims

### Claim 1

An integrated circuit, comprising:
a transistor including a source, a drain, and a gate located between the source and the drain, wherein a metallic member is connected to the source and extends toward the drain over the gate, the metallic member including a side facing the drain and terminated between the gate and the drain; and
a capacitor including a first structure made of a metallic layer, a second structure made of the metallic layer, and a dielectric layer laterally disposed between the first structure and the second structure, wherein the first structure is connected to the metallic member and extended above the metallic member, and the second structure is electrically connected to and located above the drain.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the dielectric layer comprises silicon nitride.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the metallic layer comprises aluminum.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the first structure and the second structure are interdigitated.

### Claim 5

A monolithic integrated circuit, comprising:
a capacitor including first and second electrodes formed of a metallic layer and an intralayer dielectric between the first and second electrodes; and
a transistor including a source, a drain, and a gate located between the source and the drain, wherein a metallic member is connected to the source and extends toward the drain over the gate, the metallic member including a side facing the drain and terminated between the gate and the drain, wherein
the first electrode is connected to the metallic member and extended above the metallic member; and
the second electrode is electrically connected to and located above the drain.

### Claim 6 (depends on 5)

The monolithic integrated circuit of claim 5, wherein the first and second electrodes of the capacitor are configured to be coupled to a high voltage power domain and a low voltage power domain coupled to a level shifter, respectively.

### Claim 7 (depends on 5)

The monolithic integrated circuit of claim 5, wherein the capacitor is configured as a feedback capacitor in a voltage or current converter.

### Claim 8 (depends on 5)

The monolithic integrated circuit of claim 5, wherein the capacitor is configured to serve for zero detection of a varying voltage.

### Claim 9 (depends on 5)

The monolithic integrated circuit of claim 5, wherein the capacitor is electrically coupled to a switch node of a power converter.

### Claim 10 (depends on 5)

The monolithic integrated circuit of claim 5, further comprising at least one of a Schmitt trigger, a logic gate, a flip-flop, a buffer, a logic control stage.

### Claim 11 (depends on 1)

The integrated circuit of claim 1, wherein the dielectric layer comprises a tetraethoxysilane (TEOS) layer contacting the first and second structures and a silicon nitride (Si3N4) layer on the TEOS layer.

### Claim 12 (depends on 1)

The integrated circuit of claim 1, wherein the dielectric layer between the first and second structures is located above a region of the transistor, the region located between the gate and the drain.

### Claim 13 (depends on 1)

The integrated circuit of claim 1, wherein the capacitor is located above the transistor.

### Claim 14 (depends on 1)

The integrated circuit of claim 1, wherein the metallic layer has a thickness greater than 1 micrometer.

### Claim 15 (depends on 1)

The integrated circuit of claim 1, wherein the metallic layer has a thickness greater than 3 micrometer.

### Claim 16 (depends on 1)

The integrated circuit of claim 1, wherein the metallic layer is a first metal layer, the integrated circuit further comprising:
third and fourth structures made of a second metal layer, wherein:
the third structure stacked on the first structure;
the fourth structure stacked on the second structure; and
the dielectric layer includes a portion between the third and fourth structure.

### Claim 17 (depends on 1)

The integrated circuit of claim 1, wherein the transistor includes a layer of III-V semiconductor material disposed on a silicon substrate.

### Claim 18 (depends on 7)

The monolithic integrated circuit of claim 7, wherein the voltage or current converter includes a DC-DC converter.

### Claim 19 (depends on 7)

The monolithic integrated circuit of claim 7, wherein the voltage or current converter includes a buck or boost converter.

### Claim 20 (depends on 5)

The monolithic integrated circuit of claim 5, wherein the transistor includes a layer of III-V semiconductor material disposed on a silicon substrate.