# US 12,113,056 B2 · Stacked dies and methods for forming bonded structures

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- Number: US 12,113,056 B2
- Document ID: US12113056B2
- Status: Granted
- Kind: B2
- Application number: 18/145,282
- Filed: 2022-12-22
- Published: 2023-04-27
- Granted: 2024-10-08
- Earliest claimed: 2016-05-19
- Assignees: Adeia Semiconductor Bonding Technologies Inc.
- Applicants: Adeia Semiconductor Bonding Technologies Inc.
- Inventors: Cyprian Emeka Uzoh; Arkalgud R. Sitaram; Paul Enquist
- Web page: https://patentgrep.com/patent/US12113056B2

## CPC

- H10W 90/00: Package configurations
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 72/70: for supporting or gripping
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 74/014: {using batch processing}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 72/072: {of bump connectors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/074: {of anisotropic conductive adhesives}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/925: {Bond pads having a filler embedded in a matrix}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

## Claims

### Claim 1

A bonded structure comprising:
a carrier;
a first die layer comprising:
a first surface and a second surface opposite the first surface, the first surface directly bonded to the carrier without an intervening adhesive, the second surface comprising a first non-conductive region and a first conductive region;
a first integrated device die; and
a first protective material comprising a first layer disposed along a sidewall of the first integrated device die and a second layer on the first layer, each of the first and second layers comprising a silicon-containing inorganic dielectric material; and
a second die layer comprising:
a third surface comprising a second non-conductive region directly bonded to the first non-conductive region and a second conductive region directly bonded to the first conductive region; and
a second integrated device die.

### Claim 2 (depends on 1)

The bonded structure of claim 1, wherein each of the first and second integrated device dies has a thickness less than 30 microns.

### Claim 3 (depends on 1)

The bonded structure of claim 1, wherein each of the first and second integrated device dies has a thickness less than 20 microns.

### Claim 4 (depends on 1)

The bonded structure of claim 1, wherein the first layer has a hardness greater than a bulk material of the first integrated device die.

### Claim 5 (depends on 4)

The bonded structure of claim 4, wherein the first layer has a hardness greater than the second layer.

### Claim 6 (depends on 1)

The bonded structure of claim 1, wherein the first layer comprises silicon nitride and the second layer comprises silicon oxide.

### Claim 7 (depends on 1)

The bonded structure of claim 1, further comprising a second protective material covering sidewalls of the second integrated device die.

### Claim 8 (depends on 7)

The bonded structure of claim 7, wherein the second protective material comprises multiple layers, each layer comprising a silicon-containing inorganic dielectric material.

### Claim 9 (depends on 8)

The bonded structure of claim 8, wherein the second protective material comprises a third layer disposed along a sidewall of the second integrated device die and a fourth layer disposed on the third layer, the third layer comprising silicon nitride and the fourth layer comprising silicon oxide.

### Claim 10 (depends on 1)

The bonded structure of claim 1, wherein the first integrated device die comprises a memory die, and wherein the second integrated device die comprises a processor die.

### Claim 11 (depends on 1)

The bonded structure of claim 1, wherein the first die layer comprises a third die, a portion of the first protective material disposed in a gap between the first integrated device die and the third die.

### Claim 12 (depends on 11)

The bonded structure of claim 11, wherein the portion of the first protective material completely fills the gap between the first integrated device die and the third die.

### Claim 13 (depends on 1)

The bonded structure of claim 1, wherein the second die layer further comprises a bonding layer between the second integrated device die and the first integrated device die, the bonding layer comprising the second non-conductive region and the second conductive region.

### Claim 14 (depends on 1)

The bonded structure of claim 1, wherein the carrier comprises a redistribution layer (RDL).

### Claim 15

A bonded structure comprising:
a first die layer comprising:
an upper surface opposite a lower surface and outer side surfaces between the upper and lower surfaces, the upper surface comprising a first non-conductive region and a first conductive region;
a first integrated device die comprising side surfaces, an active side at a lower surface of the first die layer, and through-substrate vias; and
a first protective material disposed on the side surfaces of the first integrated device die; and
a second die layer comprising:
an upper surface opposite a lower surface, and outer side surfaces between the upper and lower surfaces; and
a second integrated device die comprising side surfaces and a bonding surface at the lower surface of the second die layer, wherein the bonding surface comprises a second non-conductive region directly bonded to the first non-conductive region and a second conductive region directly bonded to the first conductive region;
a third die spaced apart from the second integrated device die by a gap; and
a second protective material disposed on the side surfaces of the second integrated device die, the second protective material including one or more inorganic insulating materials completely filling the gap between the second integrated device die and the third die,
wherein the outer side surfaces of the first and second die layers are aligned in a manner characteristic of singulation after forming the first and second protective materials and directly bonding the second integrated device die to the upper surface of the first die layer.

### Claim 16 (depends on 15)

The bonded structure of claim 15, wherein the first protective material comprises multiple layers, each layer comprising a silicon-containing inorganic dielectric material.

### Claim 17 (depends on 15)

The bonded structure of claim 15, wherein the second non-conductive region is directly bonded to the first non-conductive region by way of a covalent bond.

### Claim 18 (depends on 15)

The bonded structure of claim 15, wherein the second protective material comprises multiple layers, each layer being a silicon-containing inorganic dielectric material.

### Claim 19 (depends on 15)

The bonded structure of claim 15, wherein each of the first and second integrated device dies has a thickness less than 20 microns.

### Claim 20 (depends on 15)

The bonded structure of claim 15, wherein the first die layer comprises a dielectric layer over the first integrated device die and the first protective material, a conductive material disposed in a cavity of the dielectric layer, the first non-conductive region comprising the dielectric layer and the first conductive region comprising the conductive material.

### Claim 21

A bonded structure comprising:
a first die having a first surface, a second surface opposite the first surface, and a side surface extending between the first and second surfaces, the first die having a through-substrate via (TSV);
a first inorganic dielectric material disposed along the side surface of the first die, the first inorganic dielectric material comprising a first inorganic dielectric layer on the side surface of the first die and a second inorganic dielectric layer on the first inorganic dielectric layer, the first inorganic dielectric layer and the second inorganic dielectric layer comprising different materials;
a dielectric layer disposed over the first surface of the first die and the first inorganic dielectric material, a conductive material disposed in a cavity of the dielectric layer, the conductive material electrically connected to the TSV;
a second die directly bonded to the dielectric layer without an adhesive, the second die including a conductive region directly bonded to the conductive material without an adhesive; and
a second inorganic dielectric material disposed over the dielectric layer and along a side surface of the second die.

### Claim 22 (depends on 21)

The bonded structure of claim 21, wherein the dielectric layer comprises a redistribution layer (RDL).

### Claim 23 (depends on 21)

The bonded structure of claim 21, further comprising a third die directly bonded to the dielectric layer, a portion of the second inorganic dielectric material completely filling a gap between the second die and the third die.

### Claim 24 (depends on 23)

The bonded structure of claim 23, wherein the first die comprises a processor die, and the second die comprises a memory die.

### Claim 25 (depends on 21)

The bonded structure of claim 21, wherein the first inorganic dielectric layer has a hardness greater than a bulk material of the first die.

### Claim 26 (depends on 25)

The bonded structure of claim 25, wherein the first inorganic dielectric layer has a hardness greater than the second inorganic dielectric layer.

### Claim 27 (depends on 21)

The bonded structure of claim 21, wherein each of the first and second inorganic dielectric layers comprises a silicon-containing material.

### Claim 28 (depends on 25)

The bonded structure of claim 25, wherein the first inorganic dielectric layer comprises silicon nitride and the second inorganic dielectric layer comprises silicon oxide.

### Claim 29 (depends on 21)

The bonded structure of claim 21, wherein each of the first and second dies has a thickness less than 20 microns.

### Claim 30 (depends on 21)

The bonded structure of claim 21, further comprising a substrate directly bonded to the second die without an intervening adhesive.

### Claim 31

A bonded structure comprising:
a first die having a first surface, a second surface opposite the first surface, and a side surface extending between the first and second surfaces;
a first inorganic dielectric material disposed along the side surface of the first die;
a dielectric layer disposed over the first surface of the first die and the first inorganic dielectric material;
a conductive interconnect at a planarized surface of the dielectric layer;
a second die directly bonded to the planarized surface of the dielectric layer and having a conductive region directly bonded to the conductive interconnect without an adhesive; and
a second inorganic dielectric material disposed over the dielectric layer and along a side surface of the second die, the second inorganic dielectric material comprising a silicon nitride layer on the side surface of the second die and a silicon oxide layer on the silicon nitride layer.

### Claim 32 (depends on 31)

The bonded structure of claim 31, wherein the first inorganic dielectric material comprises multiple layers, each layer comprising a silicon-containing inorganic dielectric material.

### Claim 33 (depends on 32)

The bonded structure of claim 32, wherein the multiple layers comprise a first layer disposed on the side surface of the first die and a second layer disposed on the first layer, the first layer comprising silicon nitride and the second layer comprising silicon oxide.

### Claim 34 (depends on 31)

The bonded structure of claim 31, wherein each of the first and second dies has a thickness less than 20 microns.

### Claim 35 (depends on 31)

The bonded structure of claim 31, wherein the first die comprises a processor die, and the second die comprises a memory die.

### Claim 36

A bonded structure, comprising:
a silicon die having outer side surfaces;
a first die layer comprising:
a first surface opposite a second surface and outer side surfaces between the first and second surfaces, wherein the first surface is coupled to the silicon die and the second surface comprises a first non-conductive region and a first conductive region;
a first integrated device die;
a second die laterally spaced apart from the first integrated device die; and
a first dielectric protective material comprising a first inorganic insulating material, wherein the first dielectric protective material is disposed on side surfaces of the first integrated device die and the second die, and the first dielectric protective material completely fills a space between the first integrated device die and the second die; and
a second die layer comprising:
a third surface opposite a fourth surface and outer side surfaces between the third and fourth surfaces, wherein the third surface comprises a second non-conductive region directly bonded to the first non-conductive region and a second conductive region directly bonded to the first conductive region;
a third integrated device die; and
a second dielectric protective material comprising a second inorganic insulating material, wherein the second dielectric protective material is disposed on side surfaces of the third integrated device die, and
wherein the outer side surfaces of the silicon die, the first die layer, and the second die layer are aligned.

### Claim 37 (depends on 36)

The bonded structure of claim 36, wherein the first dielectric protective material comprises silicon oxide.

### Claim 38 (depends on 36)

The bonded structure of claim 36, wherein the second dielectric protective material comprises silicon oxide.

### Claim 39 (depends on 36)

The bonded structure of claim 36, wherein the second die is an integrated device die.

### Claim 40 (depends on 36)

The bonded structure of claim 36, wherein the first surface of the first die layer is directly bonded to the silicon die.

### Claim 41 (depends on 36)

The bonded structure of claim 36, wherein the first non-conductive region and the first conductive region of the first die layer are on the first integrated device die.

### Claim 42 (depends on 36)

The bonded structure of claim 36, wherein the third integrated device die comprises a through-substrate via electrically coupled with the second conductive region.

### Claim 43 (depends on 42)

The bonded structure of claim 42, further comprising a redistribution layer between the through-substrate via and the second conductive region.

### Claim 44 (depends on 36)

The bonded structure of claim 36, wherein an active surface of the third integrated device die is at the third surface of the second die layer.

### Claim 45 (depends on 36)

The bonded structure of claim 36, wherein the first dielectric protective material and the second dielectric protective material define the outer side surfaces of the first die layer and the second die layer, respectively.

### Claim 46 (depends on 1)

The bonded structure of claim 1, wherein the first die layer comprises a dielectric bonding layer that defines the first surface and wherein the dielectric bonding layer is in direct contact with the carrier.

### Claim 47 (depends on 1)

The bonded structure of claim 1, wherein the second integrated device die comprises active circuitry, a via, and opposing front and back surfaces, wherein the active circuitry is closer to the front surface than the back surface, wherein the back surface faces the first die layer and the front surface faces away from the first die layer.

### Claim 48 (depends on 15)

The bonded structure of claim 15, wherein the active side faces away from the second die layer.

### Claim 49 (depends on 21)

The bonded structure of claim 21, wherein the first die comprises active circuitry that is closer to the first surface than the second surface.

### Claim 50 (depends on 21)

The bonded structure of claim 21, wherein the conductive material is directly connected to the TSV.

### Claim 51 (depends on 31)

The bonded structure of claim 31, wherein the first die comprises active circuitry and a via, wherein the active circuitry is closer to the second surface than the first surface.

### Claim 52 (depends on 36)

The bonded structure of claim 36, wherein the third integrated device die comprises active circuitry and a via, wherein the active circuitry is closer to the fourth surface of the first die layer than the third surface.

### Claim 53 (depends on 52)

The bonded structure of claim 52, wherein the via is electrically connected to the first conductive region.