# US 12,113,055 B2 · Stress reduction apparatus and method

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- Number: US 12,113,055 B2
- Document ID: US12113055B2
- Status: Granted
- Kind: B2
- Application number: 16/907,597
- Filed: 2020-06-22
- Published: 2020-10-08
- Granted: 2024-10-08
- Earliest claimed: 2012-09-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yao-Chun Chuang; Yu-Chen Hsu; Hao Chun Liu; Chita Chuang; Chen-Cheng Kuo; Chen-Shien Chen
- Web page: https://patentgrep.com/patent/US12113055B2

## CPC

- H10W 90/00: Package configurations
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 72/01: {Manufacture or treatment}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/283: {Reinforcing structures, e.g. bump collars}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

## Claims

### Claim 1

A structure comprising:
a first integrated circuit die, the first integrated circuit die comprising:
a substrate; and
a protection layer over the substrate;
an under bump metallization structure over the protection layer;
a connector attached to the under bump metallization structure;
a first dummy plane over the protection layer, wherein a sidewall of the first dummy plane is coplanar with a first sidewall of the protection layer, the first dummy plane being conductive; and
a second dummy plane over the protection layer, wherein a sidewall of the second dummy plane is coplanar with a second sidewall of the protection layer, the second dummy plane being conductive, wherein the first dummy plane and the second dummy plane form a triangular region, and wherein the connector is located in the triangular region.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the first dummy plane and the second dummy plane comprise a same conductive material.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the first dummy plane has a length in a range from about 20 μm to about 500 μm.

### Claim 4 (depends on 1)

The structure of claim 1, further comprising a second integrated circuit die electrically coupled to the first integrated circuit die through the connector.

### Claim 5 (depends on 4)

The structure of claim 4, wherein an edge of the first dummy plane is separated apart from an edge of the second integrated circuit die by a first distance along a direction parallel to a major surface of the second integrated circuit die, and wherein the first distance is greater than 50 μm.

### Claim 6 (depends on 4)

The structure of claim 4, further comprising an underfill layer between the first integrated circuit die and the second integrated circuit die, wherein the underfill layer is in physical contact with a sidewall of the connector, a sidewall of the under bump metallization structure, and a top surface of the first dummy plane.

### Claim 7 (depends on 1)

The structure of claim 1, wherein a top surface of the first dummy plane is level with a top surface of the under bump metallization structure.

### Claim 8

A structure comprising:
a first integrated circuit die, the first integrated circuit die comprising:
a substrate;
an interconnect structure over the substrate; and
a protection layer over the interconnect structure;
a connector over the protection layer and electrically coupled to the interconnect structure; and
a plurality of L-shaped dummy conductive regions over the protection layer, wherein corners of the plurality of L-shaped dummy conductive regions are aligned with respective corners of the first integrated circuit die in a plan view, and wherein the connector is located in a triangular region formed by a first L-shaped dummy conductive region of the plurality of L-shaped dummy conductive regions.

### Claim 9 (depends on 8)

The structure of claim 8, wherein the protection layer comprises a polymer material.

### Claim 10 (depends on 8)

The structure of claim 8, wherein the plurality of L-shaped dummy conductive regions comprise copper.

### Claim 11 (depends on 8)

The structure of claim 8, further comprising a second integrated circuit die, wherein the connector mechanically and electrically couples to the second integrated circuit die to the first integrated circuit die.

### Claim 12 (depends on 11)

The structure of claim 11, further comprising an underfill layer surrounding the connector, wherein the underfill layer is in physical contact with a sidewall and a top surface of the first L-shaped dummy conductive region.

### Claim 13 (depends on 8)

The structure of claim 8, further comprising an under bump metallization structure over and extending through the protection layer, wherein the under bump metallization structure electrically couples the connector to the interconnect structure.

### Claim 14 (depends on 8)

The structure of claim 8, wherein a portion of the connector extends below a top surface of the protection layer.

### Claim 15

A structure comprising:
a first integrated circuit die, the first integrated circuit die comprising:
a substrate; and
a polymer layer over the substrate;
an under bump metallization structure over the polymer layer;
a connector bonded to the under bump metallization structure;
a first dummy plane over the polymer layer and adjacent to the under bump metallization structure, wherein an edge of the first dummy plane is collinear with a first edge of the polymer layer in a plan view; and
a second dummy plane over the polymer layer and adjacent to the first dummy plane, wherein an edge of the second dummy plane is collinear with a second edge of the polymer layer in the plan view, wherein the first dummy plane and the second dummy plane form a triangular region, and wherein the connector is disposed in the triangular region, wherein the first dummy plane and the second dummy plane are conductive.

### Claim 16 (depends on 15)

The structure of claim 15, further comprising a second integrated circuit die bonded to the first integrated circuit die, wherein the connector is interposed between the first integrated circuit die and the second integrated circuit die.

### Claim 17 (depends on 16)

The structure of claim 16, further comprising an underfill layer between the first integrated circuit die and the second integrated circuit die, wherein the underfill layer is interposed between a sidewall of the under bump metallization structure and a sidewall of the first dummy plane.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the underfill layer extends across an interface between the under bump metallization structure and the connector.

### Claim 19 (depends on 17)

The structure of claim 17, wherein the underfill layer is in physical contact with a sidewall of the second integrated circuit die.

### Claim 20 (depends on 17)

The structure of claim 17, wherein the underfill layer is in physical contact with a top surface of the polymer layer.