# US 12,113,051 B2 · Die to die interface circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,051 B2 - Document ID: US12113051B2 - Status: Granted - Kind: B2 - Application number: 18/301,817 - Filed: 2023-04-17 - Published: 2023-08-17 - Granted: 2024-10-08 - Earliest claimed: 2020-09-03 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Tze-Chiang Huang; King-Ho Tam; Yu-Hao Liu - Web page: https://patentgrep.com/patent/US12113051B2 ## CPC - H10W 90/00: Package configurations - H10W 20/427: {Power or ground buses} - H10W 72/07254: {changes in dispositions} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed herein are related to an integrated circuit including multiple dies stacked along a direction. In one aspect, the integrated circuit includes a first die, a second die, and a third die stacked along the direction. In one aspect, the first die includes a first interface circuit to generate a signal. In one aspect, the second die includes a second interface circuit to receive the signal from the first interface circuit and generate a replicate signal of the signal. In one aspect, the third die includes a third interface circuit to receive the replicate signal from the second interface circuit. ## Claims ### Claim 1 An integrated circuit comprising: a first die including a first interface circuit; a second die disposed above and operatively coupled to the first die, and including a second interface circuit; and a third die disposed below and operatively coupled to the first die, and including a third interface circuit; wherein each of the first to third interface circuits is configured to propagate a signal between a first metal rail and a second metal rail of a corresponding one of the first to third dies, while being configured to electrically isolate between an electrical load of the first metal rail and an electrical load of the second metal rail of any other one of the first to third dies. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the first die comprises a first front layer and a first back layer; the second die comprises a second front layer and a second back layer, the second front layer facing the first back layer; and the third die comprises a third front layer and a third back layer, the third back layer facing the first front layer. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the first interface circuit is disposed in the first back layer, with the first metal rail and the second metal rail of the first die extending through the first front layer and the first back layer, respectively. ### Claim 4 (depends on 2) The integrated circuit of claim 2, wherein the second interface circuit is disposed in the second back layer, with the first metal rail and the second metal rail of the second die extending through the second front layer and the second back layer, respectively. ### Claim 5 (depends on 2) The integrated circuit of claim 2, wherein the third interface circuit is disposed in the third back layer, with the first metal rail and the second metal rail of the third die extending through the third front layer and the third back layer, respectively. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the signal is a data signal, wherein the first to third interface circuits each include a first buffer circuit. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein the first buffer circuit of the first interface circuit is configured to: receive the data signal through the corresponding second metal rail; generate a replicate data signal of the data signal; and transmit the replicate data signal to the third interface circuit through the corresponding first metal rail. ### Claim 8 (depends on 6) The integrated circuit of claim 6, wherein the first to third interface circuits each include a second buffer circuit. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the second buffer circuit of the first interface circuit is configured to: receive a clock signal through the corresponding second metal rail; generate a replicate clock signal of the clock signal; and transmit the replicate clock signal to the third interface circuit through the corresponding first metal rail. ### Claim 10 An integrated circuit comprising: a first die including a first front layer and a first back layer, with a first interface circuit disposed in the first back layer; a second die including a second front layer and a second back layer, with a second interface circuit disposed in the second back layer; and a third die including a third front layer and a third back layer, with a third interface circuit disposed in the third back layer; wherein each of the first to third interface circuits is configured to propagate a signal between a first metal rail and a second metal rail of a corresponding one of the first to third dies, while being configured to electrically isolate between an electrical load of the first metal rail and an electrical load of the second metal rail of any other one of the first to third dies. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the second die is disposed above and operatively coupled to the first die with the first back layer facing the second front layer, and the third die disposed below and operatively coupled to the first die with the third back layer facing the first front layer. ### Claim 12 (depends on 10) The integrated circuit of claim 10, wherein the first metal rail and the second metal rail of the first die extend through the first front layer and the first back layer, respectively. ### Claim 13 (depends on 10) The integrated circuit of claim 10, wherein the first metal rail and the second metal rail of the second die extend through the second front layer and the second back layer, respectively. ### Claim 14 (depends on 10) The integrated circuit of claim 10, wherein the first metal rail and the second metal rail of the third die extend through the third front layer and the third back layer, respectively. ### Claim 15 (depends on 10) The integrated circuit of claim 10, wherein the signal is a data signal, wherein the first to third interface circuits each include a first buffer circuit. ### Claim 16 (depends on 15) The integrated circuit of claim 15, wherein the first buffer circuit of the first interface circuit is configured to: receive the data signal through the corresponding second metal rail; generate a replicate data signal of the data signal; and transmit the replicate data signal to the third interface circuit through the corresponding first metal rail. ### Claim 17 (depends on 15) The integrated circuit of claim 15, wherein the first to third interface circuits each include a second buffer circuit. ### Claim 18 (depends on 17) The integrated circuit of claim 17, wherein the second buffer circuit of the first interface circuit is configured to: receive a clock signal through the corresponding second metal rail; generate a replicate clock signal of the clock signal; and transmit the replicate clock signal to the third interface circuit through the corresponding first metal rail.