# US 12,113,050 B2 · Semiconductor package with increased thermal radiation efficiency

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- Number: US 12,113,050 B2
- Document ID: US12113050B2
- Status: Granted
- Kind: B2
- Application number: 17/552,614
- Filed: 2021-12-16
- Published: 2022-09-15
- Granted: 2024-10-08
- Earliest claimed: 2021-03-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sang-Sick Park; Un-Byoung Kang; Jongho Lee; Teak Hoon Lee
- Web page: https://patentgrep.com/patent/US12113050B2

## CPC

- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 90/00: Package configurations
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07354: {changes in dispositions}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/265: {Providing thermal transfer, e.g. thermal bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/965: {Providing thermal transfer}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

## Claims

### Claim 1

A semiconductor package, comprising:
a first die having a signal region and a dummy region that surrounds the signal region, wherein the signal region is disposed in a center of the first die, and wherein the first die includes a plurality of first vias disposed in the signal region;
a second die stacked on the first die, wherein the second die includes a plurality of second vias disposed in the signal region, and wherein the second vias are positioned corresponding to the first vias;
a plurality of first die pads disposed in the signal region and on a top surface of the first die, wherein the first die pads are coupled to the first vias, and wherein each of the first die pads has a circular planar shape;
a plurality of first connection terminals disposed between the first die and the second die on the first die pads, wherein the first connection terminal couple the second vias to the first vias;
a plurality of second die pads disposed in the dummy region on the top surface of the first die and including a plurality of corner die pads and a plurality of lateral die pads, wherein each of the second die pads has a rectangular planar shape; and
a plurality of second connection terminals disposed between the first die and the second die on the second die pads, wherein the second connection terminals are electrically insulated from both the first vias and the second vias,
wherein the corner die pads are radially arranged adjacent to a corner of the second die, and wherein each of the corner die pads has a major axis that is oriented towards a center of the second die.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein a long side of the signal region extends in a first direction inside the dummy region.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein, when viewed in a plan view, the dummy region includes a first dummy region adjacent to a corner of the first die and a second dummy region adjacent to a lateral surface of the first die, and
wherein,
in the first dummy region, the major axes of the corner die pads are directed toward the corner of the first die, and
in the second dummy region, the major axes of the lateral die pads are directed toward the lateral surface of the first die.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein planar shapes of one or more of the corner die pads in the first dummy region are rotationally shifted about 45 degrees with respect to the planar shapes of the lateral die pads in the second dummy region.

### Claim 5 (depends on 3)

The semiconductor package of claim 3, wherein,
in the first dummy region, the second die pads are arranged along a direction that leads toward the lateral surface of the first die, and
in the second dummy region, the second die pads are arranged along a direction that leads toward the corner of the first die.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, further comprising a plurality of third die pads disposed in the dummy region and on a bottom surface of the second die,
wherein the second connection terminals connect the second die pads to the third die pads, and
wherein each of the third die pads has a planar shape that is the same as a planar shape of a corresponding second die pad.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein each of the third die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, further comprising an under-fill that fills a space between the first die and the second die,
wherein the under-fill surrounds the first die pads, the first connection terminals, the second die pads, and the second connection terminals.

### Claim 9

A semiconductor package, comprising:
a substrate;
a plurality of dies vertically stacked on the substrate;
an under-fill that fills a space between the dies;
a molding layer disposed on the substrate and at least partially covering the dies; and
a plurality of external terminals on a bottom surface of the substrate,
wherein each of the dies includes:
a plurality of vias that vertically penetrate the dies;
a plurality of first pads disposed on a top surface of the dies and coupled to the vias; and
a plurality of second pads and a plurality of third pads both disposed on the top surface of the dies and electrically separated from the vias, wherein each of the second and third pads has a rectangular planar shape,
wherein the first pads are disposed in the center of each of the dies,
wherein the second pads are disposed adjacent to corners of the dies and arranged radially,
wherein each of the first pads has a circular planar shape,
wherein each of the second pads has a rectangular planar shape whose major axis is oriented towards a center of the substrate,
wherein a lateral surface of each of the second pads is directed toward the corners of the dies,
wherein the third pads are disposed adjacent to lateral surfaces of the dies, and
wherein a lateral surface of each of the third pads is directed toward the lateral surfaces of the dies.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein
the first pads are disposed in central portions of the dies, and
the vias of the dies are connected to each other through first connection terminals disposed on the first pads.

### Claim 11 (depends on 9)

The semiconductor package of claim 9, wherein the major axis of one or more of the second pads is rotated about 45 degrees relative to the major axis of the third pad.

### Claim 12 (depends on 9)

The semiconductor package of claim 9, wherein,
the first pads are disposed in a signal region on a central portion of the die, and
wherein the second pads and the third pads are disposed in a dummy region that surrounds the signal region when viewed in a plan view.

### Claim 13 (depends on 9)

The semiconductor package of claim 9, wherein
the second pads are arranged along a direction that leads toward the lateral surface of the die, and
wherein the third pads are arranged along a direction that leads toward the corner of the die.

### Claim 14 (depends on 9)

The semiconductor package of claim 9, further comprising:
a plurality of first connection terminals disposed on the first pads;
a plurality of second connection terminals disposed on the second pads; and
a plurality of third connection terminals disposed on the third pads,
wherein the dies are electrically connected to each other through the first connection terminals, and
wherein, between the dies, the under-fill surrounds the first connection terminals, the second connection terminals, and the third connection terminals.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein each of the second and third connection terminals has a rectangular planar shape,
wherein lateral surfaces of the second connection terminals are directed toward the corners of the dies, and
wherein lateral surfaces of the third connection terminals are directed toward the lateral surfaces of the dies.

### Claim 16

A semiconductor package, comprising:
a first die including a plurality of first vias disposed in a first central portion of the first die, a plurality of first pads coupled to the first vias, and a plurality of second pads electrically separated from the first vias;
a second die stacked on the first die, the second die including a plurality of second vias disposed in a second central portion of the second die, a plurality of third pads coupled to the second vias, and a plurality of fourth pads electrically separated from the second vias, wherein the second vias are positioned to correspond to the first vias;
a plurality of first connection terminals that connect the first pads to the third pads; and
a plurality of second connection terminals that connect the second pads to the fourth pads,
wherein each of the first and third pads has a circular planar shape,
wherein each of the second and fourth pads has a rectangular planar shape,
wherein the second pads are arranged radially from the first central portion of the first die, and wherein each of the second pads has a rectangular planar shape whose major axis is oriented toward the first central portion of the first die, and
wherein the fourth pads are arranged radially from the second central portion of the second die, and wherein each of the fourth pads has a rectangular planar shape whose major axis is oriented toward the second central portion of the second die.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein,
the second pads are disposed in a first outer portion that surrounds the first central portion of the first die,
wherein lateral surfaces of the second pads are directed toward the first central portion of the first die,
wherein the fourth pads are disposed in a second outer portion that surrounds the second central portion of the second die, and
wherein lateral surfaces of the fourth pads are directed toward the second central portion of the second die.