# US 12,113,049 B2 · Semiconductor package and method of manufacturing semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,049 B2 - Document ID: US12113049B2 - Status: Granted - Kind: B2 - Application number: 18/490,172 - Filed: 2023-10-19 - Published: 2024-02-08 - Granted: 2024-10-08 - Earliest claimed: 2021-05-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chulwoo Kim - Web page: https://patentgrep.com/patent/US12113049B2 ## CPC - H10W 70/611: {for connecting multiple chips together} - H10W 90/00: Package configurations - H10P 72/74: {using temporarily an auxiliary support} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7418: {of passive members, e.g. a chip mounting substrate} - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions. ## Claims ### Claim 1 A semiconductor package, comprising: a package substrate; an interposer on the package substrate, the interposer including individual mounting regions on a first surface thereof and a plurality of first bonding pads in the individual mounting regions respectively; a plurality of semiconductor devices in the individual mounting regions on the first surface of the interposer, respectively, the plurality of semiconductor devices each having chip pads electrically connected to the plurality of first bonding pads; first conductive connection members between the plurality of first bonding pads and the chip pads; and a molding member on the interposer, the molding member covering the plurality of semiconductor devices and filling gaps between the first surface of the interposer and the plurality of semiconductor devices, the molding member directly contacting the first surface of the interposer and a bottom surface of the plurality of semiconductor devices, wherein at least one of the individual mounting regions includes a pad-free region with a cross shape and a plurality of pad regions defined by the pad-free region, and the plurality of first bonding pads are in the plurality of pad regions. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the pad-free region comprises: at least one transverse passage portion extending in a first direction; and at least one longitudinal passage portion extending in a second direction to intersect with the at least one transverse passage portion. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein, in a corresponding individual mounting region among the at least one of the individual mounting regions, the pad-free region comprises a transverse passage portion extending in a first direction and a longitudinal passage portion extending in a second direction to intersect with the transverse passage portion, and the transverse passage portion and the longitudinal passage portion cross each other in a central region of the corresponding individual mounting region to form an intersection portion. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein, in the corresponding individual mounting region, the transverse passage portion includes a first transverse extension portion and a second transverse extension portion, the first transverse extension portion extends from a first side portion of the corresponding individual mounting region to the intersection portion, the second transverse extension portion extends from a second side portion of the corresponding individual mounting region to the intersection portion, and the first side portion is opposite the second side portion. ### Claim 5 (depends on 3) The semiconductor package of claim 3, wherein in the corresponding individual mounting region, the longitudinal passage portion includes a first longitudinal extension portion and a second longitudinal extension portion, the first longitudinal extension portion extends from a third side portion of the corresponding individual mounting region to the intersection portion, and the second longitudinal extension portion extends from a fourth side portion of the corresponding individual mounting region to the intersection portion, and the fourth side portion is opposite the third side portion. ### Claim 6 (depends on 2) The semiconductor package of claim 2, wherein widths of the transverse passage portion and the longitudinal passage portion vary along extension directions thereof. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein a width of the pad-free region is at least three times a pitch between the first bonding pads. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the molding member exposes upper surfaces of the plurality of semiconductor devices. ### Claim 9 (depends on 1) The semiconductor package of claim 1, further comprising: a plurality of second conductive connection members, wherein the package substrate includes substrate pads, the interposer includes second bonding pads on a second surface of the interposer, the plurality of second conductive connection members are between the second bonding pads of the interposer and the substrate pads of the package substrate, wherein the second surface of the interposer is opposite the first surface of the interposer. ### Claim 10 (depends on 1) The semiconductor package of claim 1, further comprising: an underfill member between the interposer and the package substrate. ### Claim 11 A semiconductor package, comprising: a package substrate; an interposer on the package substrate, the interposer including a plurality of first bonding pads on a first surface of the interposer and a plurality of second bonding pads on a second surface of the interposer, the first surface of the interposer and the second surface of the interposer being opposite each other, the plurality of first bonding pads being in individual mounting regions on the first surface of the interposer, respectively; a plurality of semiconductor devices in the individual mounting regions on the first surface of the interposer, respectively, each of the plurality of semiconductor devices having chip pads electrically connected to the plurality of first bonding pads by a plurality of first conductive connection members; and a molding member on the first surface of the interposer, the molding member covering the plurality of semiconductor devices and filling gaps between the first surface of the interposer and the plurality of semiconductor devices, the molding member directly contacting the first surface of the interposer and a bottom surface of the plurality of semiconductor devices, wherein at least one of the individual mounting regions includes a pad-free region, the pad-free region has a transverse passage portion and a longitudinal passage portion crossing each other and a plurality of pad regions defined by the pad-free region, the plurality of first bonding pads are in the plurality of pad regions, the plurality of first bonding pads are not arranged in the pad-free region, and a width of the pad-free region is at least three times a pitch between the plurality of first bonding pads. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the transverse passage portion and the longitudinal passage portion cross each other in a central region of the at least one of the individual mounting regions to form an intersection portion. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein, in a corresponding individual mounting region among the at least one of the individual mounting regions, the transverse passage portion includes a first transverse extension portion and a second transverse extension portion, the first transverse extension portion extends from a first side portion of the corresponding individual mounting region to the intersection portion, the second transverse extension portion extends from a second side portion of the corresponding individual mounting region to the intersection portion, and the first side portion is opposite the second side portion. ### Claim 14 (depends on 12) The semiconductor package of claim 12, wherein, in a corresponding individual mounting region among the at least one of the individual mounting regions, the longitudinal passage portion includes a first longitudinal extension portion and a second longitudinal extension portion, the first longitudinal extension portion extends from a third side portion of the individual mounting region to the intersection portion, the second longitudinal extension portion extends from a fourth side portion of the corresponding individual mounting region to the intersection portion, and the fourth side portion is opposite the third side portion. ### Claim 15 (depends on 11) The semiconductor package of claim 11, wherein widths of the transverse passage portion and the longitudinal passage portion vary along extension directions thereof. ### Claim 16 (depends on 11) The semiconductor package of claim 11, wherein the transverse passage portion and the longitudinal passage portion intersect at an angle. ### Claim 17 (depends on 11) The semiconductor package of claim 11, wherein the molding member exposes upper surfaces of the semiconductor devices. ### Claim 18 (depends on 11) The semiconductor package of claim 11, further comprising: a plurality of second conductive connection members, wherein the package substrate includes substrate pads, and the plurality of second conductive connection members are between the second bonding pads of the interposer and the substrate pads of the package substrate. ### Claim 19 (depends on 11) The semiconductor package of claim 11, further comprising: an underfill member between the interposer and the package substrate. ### Claim 20 A semiconductor package, comprising: a package substrate including substrate pads; an interposer on the package substrate, the interposer having a plurality of first bonding pads on a first surface of the interposer and a plurality of second bonding pads on a second surface of the interposer, the first surface of the interposer and the second surface of the interposer being opposite each other, the plurality of first bonding pads being in individual mounting regions on the first surface of interposer, respectively; a plurality of semiconductor devices in the individual mounting regions on the first surface of the interposer, respectively, each of the plurality of semiconductor devices having chip pads electrically connected to the plurality of first bonding pads by a plurality of first conductive connection members; a molding member on the first surface of the interposer, the molding member covering the plurality of semiconductor devices and filling gaps between the first surface of the interposer and the plurality of semiconductor devices, the molding member directly contacting the first surface of the interposer and a bottom surface of the plurality of semiconductor devices; a plurality of second conductive connection members between the plurality of second bonding pads of the interposer and the substrate pads of the package substrate; and an underfill member between the interposer and the package substrate, wherein at least one of the individual mounting regions includes a pad-free region, the pad-free region has a transverse passage portion and a longitudinal passage portion crossing each other and a plurality of pad regions defined by the pad-free region, the first bonding pads are in the plurality of pad regions, the first bonding pads are not arranged in the pad-free region, a width of the pad-free region is at least three times a pitch between the plurality of first bonding pads, and the at least one of the individual mounting regions has an area of 11 mm×11 mm or more.