# US 12,113,048 B2 · Microelectronic assemblies

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- Number: US 12,113,048 B2
- Document ID: US12113048B2
- Status: Granted
- Kind: B2
- Application number: 18/090,801
- Filed: 2022-12-29
- Published: 2023-05-04
- Granted: 2024-10-08
- Earliest claimed: 2018-06-14
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Adel A. Elsherbini; Feras Eid; Johanna M. Swan; Shawna M. Liff
- Web page: https://patentgrep.com/patent/US12113048B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/2125: {Top-view shapes}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

## Claims

### Claim 1

A microelectronic assembly, comprising:
a package substrate;
a first insulating material layer above the package substrate, the first insulating material layer having a first lateral width;
a first die in the first insulating material layer, the first die having a top side opposite a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall laterally opposite the first sidewall;
a first interconnect in the first insulating material layer, the first interconnect laterally spaced apart from the first sidewall of the first die;
a second interconnect in the first insulating material layer, the second interconnect laterally spaced apart from the second sidewall of the first die;
a redistribution layer over the first insulating material and over the first die, the redistribution layer coupled to the first interconnect, the redistribution layer coupled to the first die, the redistribution layer coupled to the second interconnect, and the redistribution layer having a second lateral width the same as the first lateral width;
a second insulating material layer over the redistribution layer, the second insulating material layer having a third lateral width, the third lateral width the same as the second lateral width;
a second die coupled to the redistribution layer, wherein the second insulating material layer surrounds and extends beyond the second die; and
a third die coupled to the redistribution layer, the third die laterally spaced apart from the second die, wherein the second insulating material layer surrounds and extends beyond the third die.

### Claim 2 (depends on 1)

The microelectronic assembly of claim 1, wherein the third die is thinner than the second die.

### Claim 3 (depends on 1)

The microelectronic assembly of claim 1, further comprising:
a fourth die above and coupled to the third die.

### Claim 4 (depends on 1)

The microelectronic assembly of claim 1, wherein the first insulating material layer has a vertical thickness the same as a vertical thickness of the first interconnect and the second interconnect.

### Claim 5 (depends on 1)

The microelectronic assembly of claim 1, wherein the first insulating material layer has a vertical thickness greater than a vertical thickness of the first interconnect and the second interconnect.

### Claim 6 (depends on 1)

The microelectronic assembly of claim 1, wherein the first interconnect and the second interconnect extend below a bottom of the first die.

### Claim 7 (depends on 1)

The microelectronic assembly of claim 1, further comprising a third interconnect laterally spaced apart from the first interconnect, and a fourth interconnect laterally spaced apart from the second interconnect.

### Claim 8 (depends on 7)

The microelectronic assembly of claim 7, wherein the third interconnect and the first interconnect have a pitch, the fourth interconnect and the second interconnect have the pitch, and the pitch is between 100 to 300 microns.

### Claim 9

A microelectronic assembly, comprising:
a package substrate;
a first insulating material layer above the package substrate, the first insulating material layer having a first side and a second side, the second side laterally opposite to the first side;
a first die in the first insulating material layer;
a first interconnect in the first insulating material layer, the first interconnect laterally spaced apart from the first die;
a second interconnect in the first insulating material layer, the second interconnect laterally spaced apart from the first die, the first die laterally between the first interconnect and the second interconnect;
a redistribution layer over the first insulating material and over the first die, the redistribution layer coupled to the first interconnect, the redistribution layer coupled to the first die, and the redistribution layer coupled to the second interconnect, the redistribution layer extending from the first side of the first insulating layer to the second side of the first insulating layer;
a second insulating material layer over the redistribution layer, the second insulating material layer extending from the first side of the first insulating layer to the second side of the first insulating layer;
a second die in the second insulating material layer, the second die coupled to the redistribution layer;
a third die in the second insulating material layer, the third die coupled to the redistribution layer, and the third die laterally spaced apart from the second die, wherein the third die is thinner than the second die; and
a fourth die above and coupled to the third die.

### Claim 10 (depends on 9)

The microelectronic assembly of claim 9, wherein the first insulating material layer has a vertical thickness the same as a vertical thickness of the first interconnect and the second interconnect.

### Claim 11 (depends on 9)

The microelectronic assembly of claim 9, wherein the first insulating material layer has a vertical thickness greater than a vertical thickness of the first interconnect and the second interconnect.

### Claim 12 (depends on 9)

The microelectronic assembly of claim 9, further comprising a third interconnect laterally spaced apart from the first interconnect, and a fourth interconnect laterally spaced apart from the second interconnect, and wherein the third interconnect and the first interconnect have a pitch, the fourth interconnect and the second interconnect have the pitch, and the pitch is between 100 to 300 microns.

### Claim 13

A microelectronic assembly, comprising:
a package substrate;
a first insulating material layer above the package substrate, the first insulating material layer having a first lateral width;
a first die in the first insulating material layer, the first die having a top side opposite a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall laterally opposite the first sidewall;
a first interconnect in the first insulating material layer, the first interconnect laterally spaced apart from the first sidewall of the first die;
a second interconnect in the first insulating material layer, the second interconnect laterally spaced apart from the second sidewall of the first die;
a redistribution layer over the first insulating material and over the first die, the redistribution layer coupled to the first interconnect, the redistribution layer coupled to the first die, and the redistribution layer coupled to the second interconnect;
a second insulating material layer over the redistribution layer, the second insulating material layer having a second lateral width, the second lateral width the same as the first lateral width;
a second die coupled to the redistribution layer, wherein the second insulating material layer surrounds and extends beyond the second die; and
a third die coupled to the redistribution layer, the third die laterally spaced apart from the second die, wherein the second insulating material layer surrounds and extends beyond the third die, wherein the third die is thinner than the second die.