# US 12,113,045 B2 · Three-dimensional stacked fan-out packaging structure and method making the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,045 B2 - Document ID: US12113045B2 - Status: Granted - Kind: B2 - Application number: 17/574,106 - Filed: 2022-01-12 - Published: 2022-08-25 - Granted: 2024-10-08 - Earliest claimed: 2021-02-20 - Assignees: SJ Semiconductor(Jiangyin) Corporation - Applicants: SJ Semiconductor(Jiangyin) Corporation - Inventors: Yenheng Chen; Chengchung Lin - Web page: https://patentgrep.com/patent/US12113045B2 ## CPC - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 72/50: Bond wires - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 90/00: Package configurations - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/01333: {in liquid form, e.g. spin coating, spray coating or immersion coating} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/073: {of die-attach connectors} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/07353: {changes in shapes} - H10W 72/07354: {changes in dispositions} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/334: {Cross-sectional shape, i.e. in side view} - H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/351: {Materials of die-attach connectors} - H10W 72/354: {comprising polymers} - H10W 72/552: {comprising metals or metalloids, e.g. silver} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/874: {On different surfaces} - H10W 72/931: {Shapes of bond pads} - H10W 72/9413: {on encapsulations} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure provides a three-dimensional stacked fan-out packaging structure and a method making the same. The structure includes: a first semiconductor chip, a first packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, an underfill layer under the second semiconductor chip, and a second packaging material layer. The formed three-dimensional stacked fan-out packaging structure can package two sets of fan-out wafers in the three-dimensional direction. A single package stacked up after die-cutting has two sets of chips in the third-direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, the integration of the package is improved, and the package volume can shrink. ## Claims ### Claim 1 A method for making a three-dimensional stacked fan-out packaging structure, comprising: providing a first supporting substrate; disposing a separation layer on the first supporting substrate; forming a second rewiring layer on the separation layer; forming a metal connection pillar on the second rewiring layer, wherein the metal connection pillar is electrically connected to the second rewiring layer; providing a first semiconductor chip and bonding the first semiconductor chip to the second rewiring layer; forming a first packaging material layer on a surface of the second rewiring layer, wherein the first packaging material layer fills a gap between the first semiconductor chip and the metal connecting pillar and packages the first semiconductor chip and the metal connecting pillar, wherein the first packaging material layer includes a first surface and a second surface opposite to the first surface, wherein the second surface of the first packaging material layer is in contact with the second rewiring layer, and the first surface of the first packaging material layer exposes the metal connecting pillar; forming a first rewiring layer on the first surface of the first packaging material layer, wherein the first rewiring layer is electrically connected to the first semiconductor chip and the metal connecting pillar; forming a solder bump on a surface of the first rewiring layer away from the first semiconductor chip, wherein the solder bump is electrically connected to the first rewiring layer; providing a second supporting substrate and bonding the second supporting substrate to the first rewiring layer; removing the first supporting substrate and the separation layer to expose the second rewiring layer; providing a second semiconductor chip and electrically connecting the second semiconductor chip to the second rewiring layer; forming an underfill layer between the second semiconductor chip and the second rewiring layer; forming a second packaging material layer on a periphery area of the second semiconductor chip; and removing the second supporting substrate. ### Claim 2 (depends on 1) The method for making the three-dimensional stacked fan-out packaging structure according to claim 1, wherein the first supporting substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; wherein the second supporting substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; and wherein the separation layer is a polymer layer or an adhesive layer, wherein the separation layer is coated on the surface of the first supporting substrate by a spin coating process, then cured and molded by an ultraviolet curing or thermal curing process. ### Claim 3 (depends on 1) The method for making the three-dimensional stacked fan-out packaging structure according to claim 1, wherein the first rewiring layer comprises a first wiring dielectric layer and a first metal wiring layer disposed in the first wiring dielectric layer, and wherein the second rewiring layer comprises a second wiring dielectric layer and a second metal wiring layer disposed in the second wiring dielectric layer; wherein a material of the first wiring dielectric layer and a material of the second wiring dielectric layer each comprises one or more of epoxy resin, silicone rubber, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphorosilicate glass, and fluorine-containing glass; and wherein a material of the first metal wiring layer and a material of the second metal wiring layer comprises one or more of copper, aluminum, nickel, gold, silver, and titanium. ### Claim 4 (depends on 3) The method for making the three-dimensional stacked fan-out packaging structure according to claim 3, wherein the forming of the first rewiring layer and the second rewiring layer comprises: forming a dielectric layer using a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form the wiring dielectric layer, and forming a metal layer on a surface of the wiring dielectric layer using a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or an electroless plating process, and etching the metal layer to form a metal wiring layer, wherein the metal connection pillar is electrically connected to the metal wiring layer. ### Claim 5 (depends on 1) The method for making the three-dimensional stacked fan-out packaging structure according to claim 1, wherein the first semiconductor chip is a first bare chip which is unpackaged or a first packaged chip, and the second semiconductor chip is a second bare chip which is unpackaged or a second packaged chip. ### Claim 6 (depends on 1) The method for making the three-dimensional stacked fan-out packaging structure according to claim 1, wherein the first semiconductor chip is a first bare chip, and the second semiconductor chip is a second bare chip, the first bare chip and the second bare chip each comprises a contact pad, a dielectric layer formed on the contact pad, and a metal pillar formed in the dielectric layer and penetrating the dielectric layer, wherein one end of the metal pillar is connected to the contact pad, and another end of the metal pillar is connected to the first rewiring layer. ### Claim 7 (depends on 1) The method for making the three-dimensional stacked fan-out packaging structure according to claim 1, wherein the first semiconductor chip is a first bare chip, and the second semiconductor chip is a second packaged chip, the first bare chip comprises a contact pad, a dielectric layer formed on the contact pad, and a metal pillar formed in the dielectric layer and penetrating the dielectric layer, wherein one end of the metal pillar is connected to the contact pad, and another end of the metal pillar is connected to the first rewiring layer, and the second packaged chip comprises a contact pad, wherein a solder connection structure is formed on the first packaged chip, and the solder connection structure comprises a metal pillar and a solder ball, wherein one end of the metal pillar is connected to the contact pad, another end of the metal pillar is connected to the solder ball, and the solder ball is connected to the first rewiring layer. ### Claim 8 (depends on 1) The method for making the three-dimensional stacked fan-out packaging structure according to claim 1, wherein the first semiconductor chip is a first packaged chip and the second semiconductor chip is a second bare chip, wherein the first packaged chip comprises a contact pad, wherein a solder connection structure is formed on the first packaged chip, and the solder connection structure comprises a metal pillar and a solder ball, wherein one end of the metal pillar is connected to the contact pad, another end of the metal pillar is connected to the solder ball, and the solder ball is connected to the first rewiring layer, and the second bare chip comprises a contact pad, a dielectric layer formed on the contact pad, and a metal pillar formed in the dielectric layer and penetrating the dielectric layer, wherein one end of the metal pillar is connected to the contact pad, and another end of the metal pillar is connected to the second rewiring layer. ### Claim 9 (depends on 1) The method for making the three-dimensional stacked fan-out packaging structure according to claim 1, wherein the first semiconductor chip is a first packaged chip and the second semiconductor chip is a second packaged chip, the first packaged chip and the second packaged chip each comprises a contact pad, wherein a solder connection structure is formed on the second packaged chip, and the solder connection structure comprises a metal pillar and a solder ball, wherein one end of the metal pillar is connected to the contact pad, another end of the metal pillar is connected to the solder ball, and the solder ball is connected to the second rewiring layer. ### Claim 10 A three-dimensional stacked fan-out packaging structure, comprising: a first semiconductor chip; a first packaging material layer, comprising a first surface and a second surface opposite to the first surface, wherein the first packaging material layer is disposed in a periphery area of the first semiconductor chip; a metal connecting pillar, disposed penetrating through the first packaging material layer; a first rewiring layer, disposed on the first surface of the first packaging material layer, and electrically connected to the first semiconductor chip and the metal connecting pillar; a second rewiring layer, disposed on the second surface of the first packaging material, and electrically connected to the metal connecting pillar, wherein the second rewiring layer electrically connects to the first rewiring layer through the metal connecting pillar, wherein the first semiconductor chip is bonded to the second rewiring layer; a second semiconductor chip, disposed on a surface of the second rewiring layer away from the first semiconductor chip, and electrically connected to the second rewiring layer; a solder ball bump, disposed on a surface of the first rewiring layer away from the first semiconductor chip, and electrically connected to the first rewiring layer; an underfill layer, disposed between the second semiconductor chip and the second rewiring layer; and a second packaging material layer, packaging the second semiconductor chip in a periphery area of the second semiconductor chip. ### Claim 11 (depends on 10) The three-dimensional stacked fan-out packaging structure according to claim 10, wherein the first semiconductor chip is a first bare chip which is unpackaged or a first packaged chip, and the second semiconductor chip is a second bare chip which is unpackaged or a second packaged chip. ### Claim 12 (depends on 10) The three-dimensional stacked fan-out packaging structure according to claim 10, wherein the first semiconductor chip is a first bare chip, and the second semiconductor chip is a second bare chip, the first bare chip and the second bare chip each comprises a contact pad, a dielectric layer formed on the contact pad, and a metal pillar formed in the dielectric layer and penetrating the dielectric layer, wherein one end of the metal pillar is connected to the contact pad, and another end of the metal pillar is connected to the first rewiring layer. ### Claim 13 (depends on 10) The three-dimensional stacked fan-out packaging structure according to claim 10, wherein the first semiconductor chip is a first bare chip, and the second semiconductor chip is a second packaged chip, the first bare chip comprises a contact pad, a dielectric layer formed on the contact pad, and a metal pillar formed in the dielectric layer and penetrating the dielectric layer, wherein one end of the metal pillar is connected to the contact pad, and another end of the metal pillar is connected to the first rewiring layer, and the second packaged chip, the first packaged chip comprises a contact pad, wherein a solder connection structure is formed on the first packaged chip, and the solder connection structure comprises a metal pillar and a solder ball, wherein one end of the metal pillar is connected to the contact pad, another end of the metal pillar is connected to the solder ball, and the solder ball is connected to the first rewiring layer. ### Claim 14 (depends on 10) The three-dimensional stacked fan-out packaging structure according to claim 10, wherein the first semiconductor chip is a first packaged chip and the second semiconductor chip is a second bare chip, wherein the first packaged chip comprises a contact pad, wherein a solder connection structure is formed on the first packaged chip, and the solder connection structure comprises a metal pillar and a solder ball, wherein one end of the metal pillar is connected to the contact pad, another end of the metal pillar is connected to the solder ball, and the solder ball is connected to the first rewiring layer, and the second bare chip comprises a contact pad, a dielectric layer formed on the contact pad, and a metal pillar formed in the dielectric layer and penetrating the dielectric layer, wherein one end of the metal pillar is connected to the contact pad, and another end of the metal pillar is connected to the second rewiring layer. ### Claim 15 (depends on 10) The three-dimensional stacked fan-out packaging structure according to claim 10, wherein the first semiconductor chip is a first packaged chip and the second semiconductor chip is a second packaged chip, the first packaged chip and the second packaged chip each comprises a contact pad, wherein a solder connection structure is formed on the second packaged chip, and the solder connection structure comprises a metal pillar and a solder ball, wherein one end of the metal pillar is connected to the contact pad, another end of the metal pillar is connected to the solder ball, and the solder ball is connected to the second rewiring layer. ### Claim 16 (depends on 10) The three-dimensional stacked fan-out packaging structure according to claim 10, wherein the first rewiring layer includes a first wiring dielectric layer and a first metal wiring layer disposed in the first wiring dielectric layer, and wherein the second rewiring layer includes a second wiring dielectric layer and a second metal wiring layer disposed in the second wiring dielectric layer; wherein a material of the first wiring dielectric layer and a material of the second wiring dielectric layer each comprises one or more of epoxy resin, silicone rubber, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphorosilicate glass, and fluorine-containing glass; and wherein a material of the first metal wiring layer and a material of the second metal wiring layer each comprises one or more of copper, aluminum, nickel, gold, silver, and titanium. ### Claim 17 (depends on 10) The three-dimensional stacked fan-out packaging structure according to claim 10, wherein the first packaging material layer comprises one or more of a polyimide layer, a silicone rubber layer, and an epoxy resin layer; wherein the second packaging material layer comprises one or more of a polyimide layer, a silicone rubber layer, and an epoxy resin layer; and wherein the underfill layer comprises an epoxy resin layer. ### Claim 18 (depends on 10) The three-dimensional stacked fan-out packaging structure according to claim 10, wherein a material of the solder ball bump comprises one or more of copper, aluminum, nickel, gold, silver, and titanium.