# US 12,113,044 B2 · Semiconductor package and manufacturing method thereof

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- Number: US 12,113,044 B2
- Document ID: US12113044B2
- Status: Granted
- Kind: B2
- Application number: 17/676,094
- Filed: 2022-02-18
- Published: 2023-08-24
- Granted: 2024-10-08
- Earliest claimed: 2022-02-18
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Shan-Bo Wang; Chin-Li Kao; An-Hsuan Hsu
- Web page: https://patentgrep.com/patent/US12113044B2

## CPC

- H10W 72/30: Die-attach connectors
- H10W 90/00: Package configurations
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/685: comprising multiple insulating layers
- H10W 72/01257: {by reflowing}
- H10W 72/016: {of strap connectors}
- H10W 72/072: {of bump connectors}
- H10W 72/07234: {Using a reflow oven}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07255: {changes in materials}
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/2524: {Eutectic alloys}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/257: {Multiple bump connectors having different materials}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/725: {between a chip and a laterally-adjacent insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.

## Claims

### Claim 1

An electrical device structure, comprising:
a first package component; and
an electrically conductive interconnector structure electrically connected to the first package component, comprising:
a first conductive pad on the first package component, a first alloy layer, and a solder layer, wherein the first alloy layer comprises a first conductive elemental material with a melting point less than a melting point of the solder layer, and the first alloy layer is closer to the first conductive pad than the solder layer is.

### Claim 2 (depends on 1)

The electrical device structure of claim 1, wherein a melting point of the first alloy layer is greater than the melting point of the solder layer.

### Claim 3 (depends on 2)

The electrical device structure of claim 2, wherein the first alloy layer comprises a second conductive elemental material, and the first conductive pad comprises the second conductive elemental material.

### Claim 4 (depends on 3)

The electrical device structure of claim 3, wherein the melting point of the first conductive elemental material is from about 20° C. to about 35° C.

### Claim 5 (depends on 4)

The electrical device structure of claim 4, wherein the solder layer is in contact with the first alloy layer, and the solder layer does not comprise the first conductive elemental material.

### Claim 6 (depends on 5)

The electrical device structure of claim 5, wherein the first conductive elemental material is gallium.

### Claim 7 (depends on 1)

The electrical device structure of claim 1, further comprising:
a second package component,
wherein the electrically conductive interconnector structure comprises a second alloy layer and a second conductive pad on the second package component, the second alloy layer is closer to the second conductive pad than the solder layer is, and the second alloy layer comprises a second conductive elemental material with a melting point less than the melting point of the solder layer.

### Claim 8 (depends on 7)

The electrical device structure of claim 7, wherein the solder layer is disposed between and in contact with the first alloy layer and the second alloy layer, and the melting point of the solder layer is less than a melting point of the first alloy layer and less than a melting point of the second alloy layer.

### Claim 9 (depends on 8)

The electrical device structure of claim 8, wherein the first conductive pad comprises a third elemental material, the first alloy layer comprises the third elemental material, the second alloy layer comprises a fourth elemental material, and the second conductive pad comprises the fourth elemental material.

### Claim 10 (depends on 9)

The electrical device structure of claim 9, wherein a thickness of the first alloy layer is less than a thickness of the solder layer.

### Claim 11 (depends on 10)

The electrical device structure of claim 10, wherein the first alloy layer and the second alloy layer are disposed on opposite sides of the solder layer, and the thickness of the first alloy layer is different from a thickness of the second alloy layer.

### Claim 12 (depends on 11)

The electrical device structure of claim 11, wherein the first alloy layer comprises metal elements the same as those of the second alloy layer.

### Claim 13 (depends on 9)

The electrical device structure of claim 9, wherein the melting point of the first conductive elemental material and the melting point of the second conductive elemental material are from about 20° C. to about 35° C.

### Claim 14 (depends on 13)

The electrical device structure of claim 13, wherein the solder layer does not comprise the first conductive elemental material and the second conductive elemental material.

### Claim 15 (depends on 14)

The electrical device structure of claim 14, wherein the first package component is spaced apart from the second package component, and the first package component is electrically connected to the second package component through the electrically conductive interconnector structure.

### Claim 16

An electrical device structure, comprising:
a substrate;
a first electronic component electrically connected on a first region of the substrate through a first interconnector; and
a second electronic component electrically connected on a second region of the substrate through a second interconnector;
wherein a first melting point of the first interconnector is greater than a second melting point of a bonding material of the second interconnector, and the first interconnector comprises a first conductive elemental material with a melting point from about 20° C. to about 35° C.

### Claim 17 (depends on 16)

The electrical device structure of claim 16, wherein the second interconnector does not comprise the first conductive elemental material.

### Claim 18 (depends on 17)

The electrical device structure of claim 17, wherein both the first interconnector and the second interconnector comprise a solder material.

### Claim 19 (depends on 16)

The electrical device structure of claim 16, wherein the first interconnector is electrically conductive and comprises a first conductive pad abutting the first electronic component, a first alloy layer, and a solder layer, wherein the first alloy layer comprises the first conductive elemental material with the melting point less than a melting point of the solder layer, the first alloy layer is closer to the first conductive pad than the solder layer is, the solder layer comprises the first conductive elemental material and a second conductive elemental material, and an amount of the second conductive elemental material is greater than that of the first conductive elemental material within the solder layer.

### Claim 20 (depends on 19)

The electrical device structure of claim 19, wherein the first conductive elemental material has an eutectic point with the second conductive elemental material.