# US 12,113,042 B2 · Metal bonding structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,042 B2 - Document ID: US12113042B2 - Status: Granted - Kind: B2 - Application number: 17/450,104 - Filed: 2021-10-06 - Published: 2022-09-29 - Granted: 2024-10-08 - Earliest claimed: 2021-03-26 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chun-Liang Lu; Wei-Lin Chen; Chun-Hao Chou; Kuo-Cheng Lee - Web page: https://patentgrep.com/patent/US12113042B2 ## CPC - H10W 72/851: {Dispositions of multiple connectors or interconnections} - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/01231: {using blanket deposition} - H10W 72/01251: {Changing the shapes of bumps} - H10W 72/01925: {in solid form} - H10W 72/01938: {in gaseous form, e.g. by CVD or PVD} - H10W 72/0198: {batch processes} - H10W 72/07236: {Soldering or alloying} - H10W 72/07252: {changes in structures or sizes} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/936: {Multiple bond pads having different shapes} - H10W 72/941: {Dispositions of bond pads} - H10W 72/957: {Multiple bond pads having different materials} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/334: {Thermocompression bonding} - H10W 80/701: {characterised by the pads after the direct bonding} - H10W 80/732: {having shape changed during the connecting} - H10W 90/792: {between multiple chips} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface. ## Claims ### Claim 1 A semiconductor structure comprising: a first wafer including a first metal structure within a body of the first wafer, wherein the first metal structure provides a first lattice structure within the body of the first wafer; a second wafer including a second metal structure within a body of the second wafer, wherein the second metal structure provides a second lattice structure within the body of the second wafer, and wherein the first wafer is coupled to the second wafer at an interface; and a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface, wherein the metal bonding structure comprises: a first plurality of metal elements that extend from the first metal structure to the interface, and a second plurality of metal elements that extend from the second metal structure to the interface, wherein the first plurality of metal elements are bonded to the second plurality of metal elements, wherein a first metal element, of the first plurality of metal elements, is bonded to a second metal element, of the second plurality of metal elements, via a solder bump, and wherein a third metal element, of the first plurality of metal elements, is bonded to a fourth metal element, of the second plurality of metal elements, without a solder bump. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein the first metal element has a first width, and wherein the second metal element has a second width that is different from the first width. ### Claim 3 (depends on 1) The semiconductor structure of claim 1, wherein the third metal element has a third width, and wherein the fourth metal element has a fourth width that is different from the third width. ### Claim 4 (depends on 1) The semiconductor structure of claim 1, wherein one or more of the first plurality of metal elements or the second plurality of metal elements includes at least one metal element that has a sloped side-surface. ### Claim 5 (depends on 4) The semiconductor structure of claim 4, wherein the at least one metal element that has the sloped side-surface comprises: a first width at a first end coupled to the first metal structure or the second metal structure, and a second width at a second end disposed at the interface, wherein the first width is greater than the second width. ### Claim 6 (depends on 1) The semiconductor structure of claim 1, wherein the first metal element extends along, and is centered on, a first logical axis from the first metal structure to the interface, wherein the second metal element extends along, and is centered on, a second logical axis from the second metal structure to the interface, and wherein the first logical axis is laterally displaced from the second logical axis. ### Claim 7 (depends on 1) The semiconductor structure of claim 1, wherein the first metal structure includes at least one metal element that is not bonded to any metal element of the second plurality of metal elements. ### Claim 8 (depends on 1) The semiconductor structure of claim 1, wherein the metal bonding structure comprises a copper-based material; and wherein the first wafer is coupled to the second wafer at the interface via a hybrid bonding region. ### Claim 9 (depends on 1) The semiconductor structure of claim 1, wherein one or more of the first wafer or the second wafer includes a system on chip or an application-specific integrated circuit. ### Claim 10 (depends on 1) The semiconductor structure of claim 1, wherein the first metal structure is embedded within the body of the first wafer at a depth that is less than a width of the first metal structure. ### Claim 11 (depends on 1) The semiconductor structure of claim 1, wherein one or more metal elements, of the first plurality of metal elements, have a different cross-sectional shape from one or more metal elements of the second plurality of metal elements. ### Claim 12 (depends on 1) The semiconductor structure of claim 1, wherein at least one metal element, of the first plurality of metal elements, has a different cross-sectional shape from at least one other metal element of the first plurality of metal elements. ### Claim 13 A method comprising: forming a first wafer that includes a first metal structure disposed within a body of the first wafer, wherein the first metal structure provides a first lattice structure within the body of the first wafer; forming a first set of recessed portions in a top surface of the first wafer; depositing a first plurality of metal elements within the first set of recessed portions; forming a second wafer including a second metal structure within a body of the second wafer, wherein the second metal structure provides a second lattice structure within the body of the second wafer; forming a second set of recessed portions in a top surface of the second wafer; depositing a second plurality of metal elements within the second set of recessed portions; depositing a solder bump on a first metal element, of the first plurality of metal elements, or a second metal element, the second plurality of metal elements; and bonding the top surface of the first wafer to the top surface of the second wafer, wherein the first plurality of metal elements are bonded to the second plurality of metal elements, wherein the first metal element is bonded to the second metal element via the solder bump, and wherein a third metal element, of the first plurality of metal elements, is bonded to a fourth metal element, of the second plurality of metal elements, without a solder bump. ### Claim 14 (depends on 13) The method of claim 13, further comprising one or more of: polishing the top surface of the first wafer after depositing the first plurality of metal elements within the first set of recessed portions; or polishing the top surface of the second wafer after depositing the second plurality of metal elements within the second set of recessed portions. ### Claim 15 (depends on 13) The method of claim 13, wherein the top surface of the first wafer and the top surface of the second wafer comprise a thermal bonding material. ### Claim 16 (depends on 13) The method of claim 13, wherein bonding the top surface of the first wafer to the top surface of the second wafer comprises: applying heat to the top surface of the first wafer and to the top surface of the second wafer to bond the top surface of the first wafer to the top surface of the second wafer. ### Claim 17 A semiconductor structure comprising: a first wafer comprising: a first metal structure that provides a first lattice structure within a body of the first wafer; and a first plurality of metal elements extending between the first metal structure and a surface of the first wafer; and a second wafer comprising: a second metal structure that provides a second lattice structure within a body of the second wafer; and a second plurality of metal elements extending between the second metal structure and a surface of the second wafer, wherein the first wafer is coupled to the second wafer at an interface, wherein the first plurality of metal elements and the second plurality of metal elements form a metal bonding structure that extends from the first metal structure to the second metal structure through the interface, wherein a first metal element, of the first plurality of metal elements, is bonded to a second metal element, of the second plurality of metal elements, via a solder bump, and wherein a third metal element, of the first plurality of metal elements, is bonded to a fourth metal element, of the second plurality of metal elements, without a solder bump. ### Claim 18 (depends on 17) The semiconductor structure of claim 17, wherein the interface comprises a hybrid bonding region. ### Claim 19 (depends on 17) The semiconductor structure of claim 17, wherein the first metal element has a first width, and wherein the second metal element has a second width that is different from the first width. ### Claim 20 (depends on 17) The semiconductor structure of claim 17, wherein the third metal element has a third width, and wherein the fourth metal element has a fourth width that is different from the third width.