# US 12,113,040 B2 · Semiconductor device

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- Number: US 12,113,040 B2
- Document ID: US12113040B2
- Status: Granted
- Kind: B2
- Application number: 17/607,359
- Filed: 2019-08-27
- Published: 2022-07-14
- Granted: 2024-10-08
- Earliest claimed: 2019-08-27
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Tomoyuki Asada; Eri Fukuda; Daisuke Tsunami
- Web page: https://patentgrep.com/patent/US12113040B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/30: Die-attach connectors
- H10W 72/071: {Connecting or disconnecting}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/07353: {changes in shapes}
- H10W 72/332: {Plan-view shape, i.e. in top view}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device according to the invention of the present application includes a support, a semiconductor chip provided on the support and a die bond material for bonding a back surface of the semiconductor chip to the support, wherein a plurality of cutouts is formed at edges formed between the back surface and side surfaces of the semiconductor chip connected to the back surface, and the die bond material is provided integrally over the plurality of cutouts.

## Claims

### Claim 1

A semiconductor device, comprising:
a support;
a semiconductor chip provided on the support; and
a die bond material for bonding a back surface of the semiconductor chip to the support,
wherein a plurality of cutouts is formed at edges formed between the back surface and side surfaces of the semiconductor chip connected to the back surface,
the die bond material is one continuous piece over the plurality of cutouts, and
each of the plurality of cutouts passes through the semiconductor chip from the back surface to an upper surface opposite to the back surface.

### Claim 2

A semiconductor device, comprising:
a support;
a semiconductor chip provided on the support; and
a die bond material for bonding a back surface of the semiconductor chip to the support, wherein
the semiconductor chip includes a transparent or semitransparent semiconductor substrate provided on the support,
a plurality of recesses is formed in an outer peripheral portion of a back surface of the semiconductor substrate, the back surface facing to the support, and
the die bond material is one continuous piece over the plurality of recesses.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein
the die bond material enters each of the plurality of recesses.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein
at least one of the plurality of recesses is formed along each side of the back surface of the semiconductor substrate.

### Claim 5 (depends on 2)

The semiconductor device according to claim 2, wherein
the plurality of recesses is formed at all edges of the back surface of the semiconductor substrate.

### Claim 6

A semiconductor device, comprising:
a support;
a semiconductor chip provided on the support; and
a die bond material for bonding a back surface of the semiconductor chip to the support, wherein
the semiconductor chip includes a semiconductor substrate provided on the support,
a plurality of recesses is formed in an outer peripheral portion of the semiconductor substrate, each of the recesses passing through the semiconductor substrate from a back surface facing to the support to an upper surface opposite to the back surface,
the semiconductor chip includes a plurality of conductors each of which is embedded in a corresponding one of the plurality of recesses from the upper surface side of the semiconductor substrate, and
the die bond material is one continuous piece over the plurality of recesses.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein
each of the plurality of conductors contacts the die bond material.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, wherein
each of the plurality of conductors is separated from an electrode of the semiconductor chip.

### Claim 9 (depends on 3)

The semiconductor device according to claim 3, wherein
at least one of the plurality of recesses is formed along each side of the back surface of the semiconductor substrate.

### Claim 10 (depends on 3)

The semiconductor device according to claim 3, wherein
the plurality of recesses is formed at all edges of the back surface of the semiconductor substrate.

### Claim 11 (depends on 4)

The semiconductor device according to claim 4, wherein
the plurality of recesses is formed at all edges of the back surface of the semiconductor substrate.

### Claim 12 (depends on 9)

The semiconductor device according to claim 9, wherein
the plurality of recesses is formed at all edges of the back surface of the semiconductor substrate.

### Claim 13 (depends on 7)

The semiconductor device according to claim 7, wherein
each of the plurality of conductors is separated from an electrode of the semiconductor chip.