# US 12,113,036 B2 · Semiconductor package and manufacturing method thereof

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- Number: US 12,113,036 B2
- Document ID: US12113036B2
- Status: Granted
- Kind: B2
- Application number: 18/342,752
- Filed: 2023-06-28
- Published: 2023-10-26
- Granted: 2024-10-08
- Earliest claimed: 2019-10-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsien-Wei Chen; Ming-Fa Chen; Sen-Bor Jan; Chih-Chia Hu
- Web page: https://patentgrep.com/patent/US12113036B2

## CPC

- H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 72/90: Bond pads, in general
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 80/016: {Cleaning}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first die and a second die. The first die includes a first coil and a second coil of an inductor. The first coil and the second coil are located at different level heights. The first coil includes a first metallic material. The second coil includes a second metallic material. The first metallic material has a different composition from the second metallic material. The second die is bonded to the first die. The second die includes a third coil of the inductor. The inductor extends from the first die to the second die.

## Claims

### Claim 1

A semiconductor package, comprising:
a first die, comprising a first winding portion and a second winding portion of an inductor, wherein the first winding portion and the second winding portion are located at different level heights, the first winding portion includes a first metallic material, the second winding portion includes a second metallic material, and the first metallic material has a different composition from the second metallic material; and
a second die bonded to the first die, comprising a third winding portion of the inductor, wherein the inductor extends from the first die to the second die.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the first die further comprises first bonding metallurgies connected to the second winding portion, the second die comprises second bonded metallurgies connected to the third winding portion, and the first bonding metallurgies directly contact the second bonding metallurgies.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the first winding portion comprises a first coil and a second coil located at different level heights, the first die further comprises a bridging portion disposed at a same level height as the second coil, wherein the second winding portion, the bridging portion, and the first bonding metallurgies are serially connected and the bridging portion comprises the first metallic material.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein the third winding portion and the second winding portion are connected in parallel to the second coil.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the third winding portion comprises the second metallic material.

### Claim 6 (depends on 3)

The semiconductor package of claim 3, wherein the second winding portion comprises a third coil and a via portion, and the first die further comprises:
a protective layer, wherein the protective layer extends between the second coil and the third coil and directly contacts the second coil at one side and the third coil at an opposite side, wherein the via portion extends through the protective layer to electrically connect the second coil and the third coil.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein the via portion directly contacts the second coil and the third coil.

### Claim 8

A semiconductor package, comprising a first die and a second die, wherein the first die comprises:
a first inductor pattern shaped as an open loop;
a second inductor pattern shaped as an open loop, connected to one end of the first inductor pattern;
a protective layer, disposed between the first inductor pattern and the second inductor pattern;
a first bonding dielectric layer, extending on and directly in contact with the second inductor pattern and the protective layer; and
first bonding pads, entrenched in the first bonding dielectric layer and levelled with a front surface of the first bonding dielectric layer;
wherein the second die comprises:
a third inductor pattern, shaped as an open loop;
a second bonding dielectric layer, extending on the third inductor pattern; and
second bonding pads, entrenched in the second bonding dielectric layer and levelled with a front surface of the second bonding dielectric layer;
wherein the front surface of the first bonding dielectric layer directly contacts the front surface of the second bonding dielectric layer, the first bonding pads directly contact the second bonding pads, and the first bonding pads and the second bonding pads connect the second inductor pattern to the third inductor pattern to form a spiraling conductive wire of an inductor comprising the first inductor pattern, the second inductor pattern, and the third inductor pattern.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the protective layer directly contacts a first metal on one side, and a second metal different from the first metal at an opposite side.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein the first inductor pattern comprises the first metal, and the second inductor pattern comprises the second metal.

### Claim 11 (depends on 8)

The semiconductor package of claim 8, wherein the first die further comprises:
a fourth inductor pattern, formed on a same side of the protective layer as the first inductor pattern; and
a bonding via directly contacting at least one of the first bonding pads at one end and extending through the protective layer to directly contact the fourth inductor pattern at an opposite end.

### Claim 12 (depends on 8)

The semiconductor package of claim 8, wherein a thickness of the third inductor pattern in a stacking direction of the second inductor pattern and the third inductor pattern is greater than a thickness of the second inductor pattern in the stacking direction of the second inductor pattern and the third inductor pattern.

### Claim 13 (depends on 8)

The semiconductor package of claim 8, wherein a pair of the first bonding pads and a pair of the second bonding pads connect the second inductor pattern to the third inductor pattern;
the first die further comprises a pair of first bonding vias connecting each end of the second inductor pattern to a respective first bonding pad of the pair of first bonding pads; and
the second die further comprises a pair of second bonding vias connecting each end of the third inductor pattern to a respective second bonding pad of the pair of second bonding pads.

### Claim 14 (depends on 8)

The semiconductor package of claim 8, wherein the first die further comprises:
a semiconductor substrate disposed over the first inductor pattern opposite to the protective layer; and
a through semiconductor via penetrating through the semiconductor substrate.

### Claim 15

A manufacturing method of a semiconductor package, comprising:
forming a first interconnection structure overlying a first semiconductor substrate and comprising a first coil of an inductor, wherein the first coil of the inductor is formed of a first conductive material;
forming a second coil of the inductor over the first coil, the second coil being electrically connected to the first coil, wherein the second coil of the inductor is formed of a second conductive material having different composition from the first conductive material;
disposing a bonding dielectric material to embed the second coil;
patterning the bonding dielectric material to form a first bonding dielectric layer, and at least one trench opening and at least one via opening in the first bonding dielectric layer;
filling a third conductive material in the at least one trench opening and the at least one via opening to form a first inductor bonding via and a first inductor bonding pad in the first bonding dielectric layer; and
bonding the first inductor bonding pad and the first bonding dielectric layer to a second inductor bonding pad and a second bonding dielectric layer, wherein after bonding, the second coil is connected to a third coil of the inductor through the first inductor bonding pad and the second inductor bonding pad.

### Claim 16 (depends on 15)

The manufacturing method of claim 15, wherein bonding the first inductor bonding pad to the second inductor bonding pad comprises contacting the first inductor bonding pad to the second inductor bonding pad and performing a thermal annealing process to bond the first inductor bonding pad to the second inductor bonding pad.

### Claim 17 (depends on 15)

The manufacturing method of claim 15, further comprising:
forming a second interconnection structure overlying a second semiconductor substrate and comprising the third coil of the inductor, wherein the third coil of the inductor is formed of a fourth conductive material;
disposing a second bonding dielectric material to cover and directly contact the third coil;
patterning the second bonding dielectric material to form the second bonding dielectric layer, and at least one trench opening and at least one via opening in the second bonding dielectric layer; and
filling a fifth conductive material in the at least one trench opening and the at least one via opening to form the second inductor bonding via and the second inductor boding pad in the second bonding dielectric layer.

### Claim 18 (depends on 15)

The manufacturing method of claim 15, further comprising:
forming conductive pads with a fourth conductive material at a same level height as the second coil, wherein the bonding dielectric material is disposed so as to embed the conductive pads together with the second coil.

### Claim 19 (depends on 15)

The manufacturing method of claim 15, wherein
a bridging portion is formed at the same level height over the first semiconductor substrate as the first coil with the first conductive material, and
the second conductive material is disposed so as to form a via portion on the second coil, wherein the via portion connects the bridging portion to the second coil.

### Claim 20 (depends on 15)

The manufacturing method of claim 15, wherein the first conductive material and the third conductive material have a same composition.