# US 12,113,031 B2 · Semiconductor device and method of making the same

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- Number: US 12,113,031 B2
- Document ID: US12113031B2
- Status: Granted
- Kind: B2
- Application number: 18/230,999
- Filed: 2023-08-07
- Published: 2023-11-30
- Granted: 2024-10-08
- Earliest claimed: 2017-11-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-Chieh Hsieh; Hau Tao; Yung-Tien Kuo
- Web page: https://patentgrep.com/patent/US12113031B2

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H01F 17/0033: {with the coil helically wound around a magnetic core}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES

## Abstract

A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

## Claims

### Claim 1

A semiconductor device, comprising:
a capacitor disposed in a first dielectric layer over an interposer substrate,
wherein the capacitor comprises a bottom electrode connected to a first contact of a wiring layer, a top electrode connected to a second contact of the wiring layer, and a second dielectric layer disposed between the bottom electrode and the top electrode,
wherein the first dielectric layer covers a top surface of the capacitor;
a via extending through the first dielectric layer electrically connected to a third contact of the wiring layer; and
a chip disposed over and electrically connected to the wiring layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the capacitor is a deep trench capacitor.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the deep trench capacitor has a trench depth of 20 μm to 50 μm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer has a thickness of 100 μm to 300 μm.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the interposer substrate is bonded to the first dielectric layer through a plurality of solder bumps.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the chip is a system on a chip.

### Claim 7

A semiconductor device, comprising:
an interposer made of a semiconductor material having a first major surface and a second major surface opposing the first major surface;
a plurality of deep trench capacitors in the second major surface of the interposer;
a plurality of passive devices formed in an inductor layer between the first major surface of the interposer and a substrate; and
a plurality of semiconductor chips disposed on the second major surface of the interposer and electrically connected to the interposer,
wherein the interposer is disposed on the substrate and is electrically connected to the substrate, and
the inductor layer is made of a different material than the interposer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the semiconductor material is silicon.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the inductor layer is made of a dielectric material.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein the inductor layer has a thickness of 50 μm to 100 μm.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, wherein the interposer has a thickness of 100 μm to 300 μm.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, wherein the deep trench capacitors have a trench depth of 20 μm to 50 μm.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, wherein the substrate is bonded to the inductor layer through a plurality of solder bumps.

### Claim 14

A semiconductor device, comprising:
an interposer having a first major surface and a second major surface opposing the first major surface;
a plurality of passive devices in the second major surface of the interposer;
a plurality of magnetic core inductors formed in an inductor layer between the first major surface of the interposer and a substrate; and
a plurality of semiconductor chips disposed over the second major surface of the interposer and electrically connected to the interposer,
wherein the interposer is disposed on the substrate and is electrically connected to the substrate, and
the inductor layer is made of a different material than the interposer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the interposer is made of a semiconductor material.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the inductor layer is made of a dielectric material.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the inductor layer has a thickness of 50 μm to 100 μm.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the interposer has a thickness of 100 μm to 300 μm.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, wherein the substrate is bonded to the inductor layer through a plurality of solder bumps.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, further comprising a wiring layer disposed between the plurality of chips and the interposer.