# US 12,113,028 B2 · Semiconductor device with integrated decoupling and alignment features

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- Number: US 12,113,028 B2
- Document ID: US12113028B2
- Status: Granted
- Kind: B2
- Application number: 17/556,149
- Filed: 2021-12-20
- Published: 2023-06-22
- Granted: 2024-10-08
- Earliest claimed: 2021-12-20
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Tse-Yao Huang
- Web page: https://patentgrep.com/patent/US12113028B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/00: Package configurations
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10W 72/0198: {batch processes}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07353: {changes in shapes}
- H10W 72/30: Die-attach connectors
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device with integrated decoupling alignment features. The semiconductor device includes a first wafer comprising a first substrate having a dielectric stack, a decoupling feature positioned in the dielectric stack under one of the plurality of first alignment marks, a plurality of first alignment marks positioned on the first substrate and parallel to each other; and a second wafer positioned on the first wafer and comprising a plurality of second alignment marks positioned above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescence material. The decoupling feature has a bottle-shaped cross-sectional profile, and the decoupling feature comprises a porous low-k material.

## Claims

### Claim 1

A semiconductor device, comprising:
a first wafer comprising:
a first substrate; and
a plurality of first alignment marks positioned on the first substrate and parallel to each other; and
a decoupling feature positioned in dielectric stack under one of the plurality of first alignment marks, and having a bottle-shaped cross-sectional profile, wherein the decoupling feature comprises a porous low-k material;
a second wafer positioned on the first wafer and comprising:
a plurality of second alignment marks positioned above the plurality of first alignment marks;
wherein the plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective;
wherein the plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescent material;
wherein the plurality of first alignment marks and the plurality of second alignment marks together configure a first set of alignment marks.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the fluorescent material comprises azobenzene.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a second set of alignment marks separated from the first set of alignment marks along a first direction;
wherein the first set of alignment marks is extending along a second direction perpendicular to the first direction, and the second set of alignment marks is extending along the first direction.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a third set of alignment marks separated from the first set of alignment marks along the second direction;
wherein the third set of alignment marks is extending along the first direction.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising a fourth set of alignment marks separated from the first set of alignment marks along a direction slanted with respective to the first direction and the second direction;
wherein the fourth set of alignment marks is extending along the second direction.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, further comprising a fifth set of alignment marks separated from the first set of alignment marks along a direction slanted with respective to the first direction and the second direction;
wherein the fifth set of alignment marks is extending along the first direction.

### Claim 7 (depends on 2)

The semiconductor device of claim 2, wherein the first wafer comprises a plurality of first conductive features horizontally surrounding the plurality of first alignment marks.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first wafer comprises a first bottom liner positioned between the plurality of first conductive features and the plurality of first alignment marks.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first wafer comprises a first top liner positioned on the plurality of first alignment marks and on the first bottom liner.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the second wafer comprises a second top liner positioned between the plurality of second alignment marks and the first top liner.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the second wafer comprises a plurality of second conductive features horizontally surrounding the plurality of second alignment marks and on the second top liner.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the second wafer comprises a second bottom liner positioned between the plurality of second alignment marks and the plurality of second conductive features, and between the plurality of second conductive features and the second top liner.

### Claim 13 (depends on 2)

The semiconductor device of claim 2, wherein the first wafer is configured as logic chips and the second wafer is configured as memory chips.

### Claim 14 (depends on 2)

The semiconductor device of claim 2, wherein the first wafer is configured as memory chips and the second wafer is configured as memory chips.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric stack comprises a first dielectric layer positioned on the substrate, a second dielectric layer positioned on the first dielectric layer, a middle dielectric layer positioned on the second dielectric layer, a third dielectric layer positioned on the middle dielectric layer, and a fourth dielectric layer positioned on the third dielectric layer, and the two second conductive features and the decoupling feature are positioned in the middle dielectric layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the third alignment mark is positioned along the fourth dielectric layer and the third dielectric layer, and is positioned on the decoupling feature.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the third alignment mark is positioned along the fourth dielectric layer and the third dielectric layer, and extends to the decoupling feature.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein a width between two valleys of sidewalls of the decoupling feature is greater than a width of a top surface of the third alignment mark.