# US 12,113,027 B2 · Three-dimensional integrated circuit structures and methods of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,027 B2 - Document ID: US12113027B2 - Status: Granted - Kind: B2 - Application number: 18/341,788 - Filed: 2023-06-27 - Published: 2023-10-19 - Granted: 2024-10-08 - Earliest claimed: 2019-03-25 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chung-Yu Lu; Ping-Kang Huang; Sao-Ling Chiu - Web page: https://patentgrep.com/patent/US12113027B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 74/01: Manufacture or treatment - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/635: {Through-vias} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01236: {in solid form, e.g. by using a powder or by laminating a foil} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps. ## Claims ### Claim 1 A device, comprising: a board substrate comprising a first group of bumps and a second group of bumps thereon: a first semiconductor package disposed over and electrically connected to the board substrate through the first group of bumps; a first underfill layer surrounding the first group of bumps; a second semiconductor package disposed over and electrically connected to the board substrate through the second group of bumps; a second underfill layer surrounding the second group of bumps; and first and second blocking walls arranged parallel to each other, located between the first and second semiconductor packages, and in direct contact a first solder mask layer on the board substrate, wherein the first solder mask layer comprises silica, barium sulfate or epoxy resin, wherein from a top view, a central part of a first sidewall of the first blocking wall is in direct contact with the first underfill layer while an edge part of the first sidewall of the first blocking wall is exposed from the first underfill layer, and a central part of a first sidewall of the second blocking wall is in direct contact with the second underfill layer while an edge part of the first sidewall of the second blocking wall is exposed from the second underfill layer. ### Claim 2 (depends on 1) The device of claim 1, wherein the first semiconductor package comprises first dies and a first encapsulation layer surrounding sidewalls of the first dies, and wherein the first underfill layer directly contacts and completely covers a sidewall of the first encapsulation layer, and is spaced apart from the first dies. ### Claim 3 (depends on 2) The device of claim 2, wherein the first semiconductor package further comprises a first interposer between the first dies and the board substrate, and the sidewall of the first encapsulation layer is flush with a sidewall of the first interposer. ### Claim 4 (depends on 1) The device of claim 1, wherein from the top view, lengths of the first and second blocking walls are greater than lengths of the first and second semiconductor packages. ### Claim 5 (depends on 1) The device of claim 1, further comprising third and fourth blocking walls arranged parallel to each other and located outside of the first and second semiconductor packages. ### Claim 6 (depends on 5) The device of claim 5, wherein from the top view, a central part of a first sidewall of the third blocking wall is in direct contact with the first underfill layer while an edge part of the first sidewall of the third blocking wall is exposed from the first underfill layer. ### Claim 7 (depends on 5) The device of claim 5, wherein the first to fourth blocking walls comprise the same insulating material. ### Claim 8 A device, comprising: a board substrate comprising a first group of bumps and a second group of bumps thereon: a first semiconductor package disposed over and electrically connected to the board substrate through the first group of bumps; a first underfill layer surrounding the first group of bumps; a second semiconductor package disposed over and electrically connected to the board substrate through the second group of bumps; a second underfill layer surrounding the second group of bumps; first and second blocking walls arranged parallel to each other and located between the first and second semiconductor packages; and third and fourth blocking walls arranged parallel to each other and located outside of the first and second semiconductor packages, wherein from the top view, a central part of a first sidewall of the first blocking wall is in direct contact with the first underfill layer while an edge part of the first sidewall of the first blocking wall is exposed from the first underfill layer, and a central part of a first sidewall of the third blocking wall is in direct contact with the first underfill layer while an edge part of the first sidewall of the third blocking wall is exposed from the first underfill layer. ### Claim 9 (depends on 8) The device of claim 8, further comprising at least one periphery device disposed over the board substrate and at an outer side of the third and fourth blocking walls. ### Claim 10 (depends on 9) The device of claim 9, wherein the at least one periphery device comprises an integrated passive device. ### Claim 11 (depends on 9) The device of claim 9, wherein the at least one periphery device comprises a dummy chip. ### Claim 12 (depends on 8) The device of claim 8, wherein the first semiconductor package comprises a first interposer, a plurality of first dies disposed on the first interposer, and a first encapsulation layer disposed on the first interposer and surrounding sidewalls of the first dies, and wherein the first underfill layer directly contacts and completely covers a sidewall of the first encapsulation layer, and is spaced apart from the first dies. ### Claim 13 (depends on 8) The device of claim 8, wherein the first to fourth blocking walls comprise the same insulating material. ### Claim 14 (depends on 8) The device of claim 8, wherein from the top view, lengths of the first to fourth blocking walls are greater than lengths of the first and second semiconductor packages. ### Claim 15 A method of forming a device, comprising: providing a board substrate; forming a first group of bumps and a second group of bumps on a first surface of the board structure; forming first and second blocking walls on the first surface of the board structure between the first group of bumps and the second group of bumps, wherein the first and second blocking walls are arranged parallel to each other, located between the first and second semiconductor packages, and in direct contact a first solder mask layer formed on the board substrate, wherein the first solder mask layer comprises silica, barium sulfate or epoxy resin; bonding a first semiconductor package to the board substrate through the first group of bumps; and forming a first underfill layer surrounding the first group of bumps and flowing to the first blocking wall, wherein from a top view, a central part of a first sidewall of the first blocking wall is in direct contact with the first underfill layer while an edge part of the first sidewall of the first blocking wall is exposed from the first underfill layer. ### Claim 16 (depends on 15) The method of claim 15, further comprising: bonding a second semiconductor package to the board substrate through the second group of bumps; and forming a second underfill layer surrounding the second group of bumps and flowing to the second blocking wall, wherein from the top view, a central part of a first sidewall of the second blocking wall is in direct contact with the second underfill layer while an edge part of the first sidewall of the second blocking wall is exposed from the second underfill layer. ### Claim 17 (depends on 15) The method of claim 15, wherein forming the first and second blocking walls comprises performing a dispensing process, an injecting process, or a spraying process. ### Claim 18 (depends on 15) The method of claim 15, further comprising, during forming the first and second blocking walls, forming third and fourth blocking walls arranged parallel to each other and located outside of the first and second semiconductor packages. ### Claim 19 (depends on 18) The method of claim 18, wherein the first to fourth blocking walls comprise the same insulating material. ### Claim 20 (depends on 18) The method of claim 18, further comprising forming at least one periphery device over the board substrate and at an outer side of the third and fourth blocking walls.