# US 12,113,023 B2 · Microelectronic structures including bridges > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,023 B2 - Document ID: US12113023B2 - Status: Granted - Kind: B2 - Application number: 17/126,502 - Filed: 2020-12-18 - Published: 2022-06-23 - Granted: 2024-10-08 - Earliest claimed: 2020-12-18 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Omkar G. Karhade; Nitin A. Deshpande - Web page: https://patentgrep.com/patent/US12113023B2 ## CPC - H10W 70/611: {for connecting multiple chips together} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 72/0198: {batch processes} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/63: Vias, e.g. via plugs - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 70/682: {comprising holes having chips therein} - H10W 72/072: {of bump connectors} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07236: {Soldering or alloying} - H10W 72/07252: {changes in structures or sizes} - H10W 72/07254: {changes in dispositions} - H10W 72/073: {of die-attach connectors} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/874: {On different surfaces} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/9413: {on encapsulations} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. ## Claims ### Claim 1 A microelectronic assembly, comprising: a microelectronic component; a substrate; and a patch structure, wherein the patch structure is coupled between the microelectronic component and the substrate, the patch structure includes an embedded bridge component, the patch structure includes a stack of conductive pillars, each pillar in the stack has a constant diameter along its length, and the diameters of the conductive pillars increase from one pillar to another in a direction from the substrate to the microelectronic component. ### Claim 2 (depends on 1) The microelectronic assembly of claim 1, wherein the patch structure is coupled to the microelectronic component by first interconnects having a first pitch and by second interconnects having a second pitch, and the first pitch is less than the second pitch. ### Claim 3 (depends on 2) The microelectronic assembly of claim 2, wherein the first interconnects are in a volume between the bridge component and the microelectronic component. ### Claim 4 (depends on 1) The microelectronic assembly of claim 1, wherein the patch structure has a first face and an opposing second face, the second face is between the first face and the microelectronic component, and the patch structure includes solder between the bridge component and the second face. ### Claim 5 (depends on 1) The microelectronic assembly of claim 1, wherein the microelectronic component is a first microelectronic component, the microelectronic assembly includes a second microelectronic component, and the patch structure is coupled between the second microelectronic component and the substrate. ### Claim 6 (depends on 5) The microelectronic assembly of claim 5, wherein the patch structure is coupled to the second microelectronic component by first interconnects having a first pitch and by second interconnects having a second pitch, and the first pitch is less than the second pitch. ### Claim 7 (depends on 1) The microelectronic assembly of claim 1, wherein the bridge component includes transistors. ### Claim 8 (depends on 1) The microelectronic assembly of claim 1, wherein the substrate includes an organic dielectric material. ### Claim 9 A microelectronic assembly, comprising: a microelectronic component; a substrate; and a patch structure, wherein the patch structure is coupled between the microelectronic component and the substrate, the patch structure has a first face and an opposing second face, the second face is between the first face and the microelectronic component, the patch structure includes an embedded bridge component, the patch structure includes a stack of conductive pillars, each pillar in the stack of conductive pillars has a constant diameter along its length, and the diameter of a conductive pillar proximate to the first face is less than the diameter of a conductive pillar proximate to the second face. ### Claim 10 (depends on 9) The microelectronic assembly of claim 9, wherein the patch structure is coupled to the microelectronic component by first interconnects having a first pitch and by second interconnects having a second pitch, and the first pitch is less than the second pitch. ### Claim 11 (depends on 10) The microelectronic assembly of claim 10, wherein the first interconnects are in a volume between the bridge component and the microelectronic component. ### Claim 12 (depends on 9) The microelectronic assembly of claim 9, wherein the patch structure includes solder between the bridge component and the second face. ### Claim 13 (depends on 9) The microelectronic assembly of claim 9, wherein the microelectronic component is a first microelectronic component, the microelectronic assembly includes a second microelectronic component, and the patch structure is coupled between the second microelectronic component and the substrate. ### Claim 14 (depends on 13) The microelectronic assembly of claim 13, wherein the patch structure is coupled to the second microelectronic component by first interconnects having a first pitch and by second interconnects having a second pitch, and the first pitch is less than the second pitch.