# US 12,113,020 B2 · Formation of metal vias on metal lines

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- Number: US 12,113,020 B2
- Document ID: US12113020B2
- Status: Granted
- Kind: B2
- Application number: 17/184,020
- Filed: 2021-02-24
- Published: 2022-08-25
- Granted: 2024-10-08
- Earliest claimed: 2021-02-24
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Ryan Scott Smith; Kai Wu; Nicolas Louis Gabriel Breil
- Web page: https://patentgrep.com/patent/US12113020B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10P 14/6329: {using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69393: {the material containing tantalum, e.g. Ta2O5}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10P 72/0454: {surrounding a central transfer chamber}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10P 14/432: {using selective deposition}
- H10P 14/44: Physical vapour deposition [PVD]
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Exemplary semiconductor processing methods include forming a via in a semiconductor structure. The via may be defined in part by a bottom surface and a sidewall surface formed in the semiconductor structure around the via. The methods may also include depositing a tantalum nitride (TaN) layer on the bottom surface of the via. In embodiments, the TaN layer may be deposited at a temperature less than or about 200° C. The methods may still further include depositing a titanium nitride (TiN) layer on the TaN layer. In embodiments, the TiN layer may be deposited at a temperature greater than or about 300° C. The methods may additionally include depositing a fill-metal on the TiN layer in the via. In embodiments, the metal may be deposited at a temperature greater than or about 300° C.

## Claims

### Claim 1

A semiconductor processing method comprising:
forming a via in a semiconductor structure, wherein the via comprises a bottom surface and sidewall surfaces formed in the semiconductor structure, wherein the bottom surface exposes a copper metal line;
depositing a tantalum nitride layer on the copper metal line exposed on the bottom surface of the via, wherein the tantalum nitride layer is deposited at a temperature less than 100° C. while contacting the copper metal line;
depositing a titanium nitride layer on the tantalum nitride layer, wherein the titanium nitride layer is deposited at a temperature greater than or about 400° C. while contacting the tantalum nitride layer; and
depositing a metal on the titanium nitride layer, wherein the metal is deposited at a temperature greater than or about 300° C.

### Claim 2 (depends on 1)

The semiconductor processing method of claim 1, wherein the tantalum nitride layer is deposited by physical vapor deposition.

### Claim 3 (depends on 1)

The semiconductor processing method of claim 1, wherein the tantalum nitride layer has a greater thickness on the bottom surface of the via than the sidewall surfaces of the via.

### Claim 4 (depends on 1)

The semiconductor processing method of claim 1, wherein the tantalum nitride layer has a thickness less than or about 60Å.

### Claim 5 (depends on 1)

The semiconductor processing method of claim 1, wherein the titanium nitride layer is deposited by atomic layer deposition.

### Claim 6 (depends on 1)

The semiconductor processing method of claim 1, wherein the titanium nitride layer has the same thickness on the bottom surface and the sidewall surfaces of the via.

### Claim 7 (depends on 1)

The semiconductor processing method of claim 1, wherein the metal deposited on the titanium nitride layer comprises tungsten.

### Claim 8 (depends on 1)

The semiconductor processing method of claim 1, wherein the metal deposited on the titanium nitride layer is deposited by chemical vapor deposition.

### Claim 9

A semiconductor processing method comprising:
forming a via on a metal line in a final metallization layer of a semiconductor structure;
forming a tantalum nitride layer in the via, wherein the tantalum nitride layer is formed directly on the final metallization layer at a temperature less than 100° C. via physical vapor deposition while contacting the final metallization layer;
forming a nucleation layer on the tantalum nitride layer in the via; and
depositing a second metal on the nucleation layer in the via.

### Claim 10 (depends on 9)

The semiconductor processing method of claim 9, wherein the metal line comprises copper.

### Claim 11 (depends on 9)

The semiconductor processing method of claim 9, wherein the nucleation layer comprises titanium nitride deposited by atomic layer deposition.

### Claim 12 (depends on 9)

The semiconductor processing method of claim 9, wherein the second metal comprises tungsten, molybdenum, cobalt, or ruthenium.

### Claim 13 (depends on 9)

The semiconductor processing method of claim 9, wherein the second metal is deposited by chemical vapor deposition at a CVD deposition temperature greater than or about 300° C.

### Claim 14 (depends on 9)

The semiconductor processing method of claim 9, wherein the via is formed through a first layer of dielectric material and a second layer of dielectric material, wherein the first layer of dielectric material comprises a silicon-oxygen-and-carbon-containing dielectric material having a thickness of greater than or about 500 Å, and the second layer of dielectric material has a thickness greater than or about 800 Å.

### Claim 15 (depends on 9)

The semiconductor processing method of claim 9, wherein the tantalum nitride layer is formed in the via using an isotropic deposition process.

### Claim 16 (depends on 9)

The semiconductor processing method of claim 9, wherein the barrier layer comprises a thickness of less than 50 Å and is characterized by a bottom surface to sidewall surface thickness ration that is greater than or about 1.5:1.

### Claim 17 (depends on 9)

The semiconductor processing method of claim 9, wherein the nucleation layer has a thickness less than or about 50 Å and is a same thickness as the tantalum nitride layer.

### Claim 18 (depends on 9)

The semiconductor processing method of claim 9, wherein the final metallization layer comprises a final back-end-of-line (BEOL) metallization layer of a logic device, and the method further comprises forming a first front-end-of-line (FEOL) metallization layer for a memory device over the logic device.

### Claim 19 (depends on 9)

The semiconductor processing method of claim 9, wherein the nucleation layer is formed at a temperature greater than or about 400° C. while contacting the tantalum nitride layer.

### Claim 20 (depends on 9)

The semiconductor processing method of claim 9, wherein the via has an aspect ratio of greater than or about 2:1 and comprises a cylindrical via shape that is tapered between a top and a bottom surface such that an area ratio between the top and the bottom surface of the via is greater than or 1.25:1.