Memory devices including strings of memory cells, and related electronic systems

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and the output device;
• and
• a memory device operably coupled to the processor device and comprising at least one microelectronic device, the at least one microelectronic device comprising:
• strings of memory cells vertically extending through a stack structure comprising vertically alternating sequences of insulative structures and conductive structures arranged in tiers;
• data lines substantially devoid of tungsten overlying the strings of memory cells, the data lines extending in a horizontal direction substantially orthogonal to an additional horizontal direction in which the conductive structures of the stack structure extend, a critical dimension of the data lines in the additional horizontal direction relatively less than a critical dimension between neighboring data lines;
• and
• interconnect structures between the strings of memory cells and the data lines, the interconnect structures comprising a beta-phase tungsten liner material substantially surrounding an alpha-phase tungsten fill material.

A memory device, comprising:

• a stack structure comprising dielectric materials and conductive materials vertically alternating with the dielectric materials;
• pillar structures comprising a channel material vertically extending through the stack structure;
• conductive contacts overlying the pillar structures;
• interconnect structures overlying the conductive contacts;
• data lines overlying the interconnect structures and operably coupled with the pillar structures through the conductive contacts and the interconnect structures;
• and
• dielectric structures overlying the data lines, at least one outer side surface of an interconnect structure, a side surface of a corresponding data line, and a side surface of a corresponding dielectric structure substantially vertically aligned with one another, and an additional, opposing outer side surface of each of the data lines and the dielectric structures substantially vertically aligned with one another.

A memory device, comprising:

• a stack structure comprising dielectric materials and conductive materials vertically alternating with the dielectric materials;
• pillar structures comprising a channel material vertically extending through the stack structure;
• conductive contacts overlying the pillar structures;
• interconnect structures overlying the conductive contacts;
• data lines overlying the interconnect structures and operably coupled with the pillar structures through the conductive contacts and the interconnect structures;
• dielectric structures overlying the data lines, at least one outer side surface of an interconnect structure, a side surface of a corresponding data line, and a side surface of a corresponding dielectric structure substantially vertically aligned with one another;
• and
• an isolation material adjacent to the pillar structures, wherein the isolation material comprises L-shaped structures individually comprising a first portion vertically extending along an additional, opposing outer side surface of the interconnect structures and a second portion extending between the first portion and the conductive contacts.