# US 12,113,018 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,018 B2 - Document ID: US12113018B2 - Status: Granted - Kind: B2 - Application number: 18/192,322 - Filed: 2023-03-29 - Published: 2023-07-20 - Granted: 2024-10-08 - Earliest claimed: 2020-03-16 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Dong Hyuk Kim; Sung Lae Oh; Tae Sung Park; Soo Nam Jung - Web page: https://patentgrep.com/patent/US12113018B2 ## CPC - H10W 20/43: Layouts of interconnections - G11C 7/18: Bit line organisation; Bit line lay-out - H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/40: characterised by the peripheral circuit region - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/42: Vias, e.g. via plugs - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction. ## Claims ### Claim 1 A semiconductor device comprising: a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction, wherein: the bit-line contact pad is one of a first group of similar-shaped bit-line contact pads disposed at a predetermined distance between adjacent ones in a first direction, the first group comprising at least one bit-line contact pad deviating from the remaining bit-line contact pads in its position in a second direction. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein: a connection pattern coupled to the deviated bit-line contact pad is different from a connection pattern coupled to the remaining bit-line contact pads of the first group. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, further comprising: a second group of bit line contact pads having a similar shape as the first group, wherein the first group and the second group are paired with each other in a second direction. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, further comprising: contact plugs that couple the bit line to its bit-line contact pad and the bit-line contact pad to a lower connection structure. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein an arrangement of a plurality of bit-line contact pads in the first group is such that a third group of bit-line contact pads is disposed symmetrical with the first group with respect to a virtual line formed along the second direction perpendicular to the first direction. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein: a plurality of bit-line contact pads are disposed in a bit-line contact region comprising two mirrored parts along the second direction orthogonal to the first direction, where the first group of bit-line contact pads is located in one part and a third group of bit-line contact pads, symmetrically mirrored the first group, is located in another part of the bit-line contact region. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the first connection pattern is formed with a line shape extending in the first direction and some portions of the first connection pattern are configured with angles or bends to interact with the deviated bit-line contact pad. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, further comprising: a conductive line, disposed in the first layer, that is not electrically connected to any bit-line contact pad. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, further comprising: a second connection pattern below the first connection pattern; a first conductive contact plug coupled to a bottom surface of the second connection pattern; a second conductive contact plug coupled between a bottom surface of the first connection pattern and a top surface of the second connection pattern; a third conductive contact plug coupled between a bottom surface of a bit-line contact pad of the first group and a top surface of the first connection pattern; and a bit-line contact coupled between the bit line and the bit-line contact pad of the first group. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, further comprising: a transistor disposed below the second connection pattern, wherein the second connection pattern is disposed over a junction region of the transistor.