# US 12,113,015 B2 · Vertical transistor fuse latches > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,015 B2 - Document ID: US12113015B2 - Status: Granted - Kind: B2 - Application number: 17/396,341 - Filed: 2021-08-06 - Published: 2023-02-09 - Granted: 2024-10-08 - Earliest claimed: 2021-08-06 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Fatma Arzum Simsek-Ege; Yuan He - Web page: https://patentgrep.com/patent/US12113015B2 ## CPC - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - G11C 17/16: using electrically-fusible links - G11C 29/76: {using address translation or modifications} - H10B 12/50: {Peripheral circuit region structures} - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Methods, systems, and devices for vertical transistor fuse latches are described. An apparatus may include a substrate and a memory array that is coupled with the substrate. The apparatus may also include a latch that is configured to store information from a fuse for the memory array. The latch may be at least partially within an additional substrate separate from and above the substrate. The latch may include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each at least partially disposed within the additional substrate above the substrate. ## Claims ### Claim 1 An apparatus, comprising: a substrate; a memory array coupled with the substrate; and a latch configured to store information from a fuse for the memory array, the latch disposed within an additional substrate above the substrate and comprising: a plurality of p-type vertical transistors comprising a first plurality of gate terminals coupled together; and a plurality of n-type vertical transistors comprising a second plurality of gate terminals coupled together. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the plurality of p-type vertical transistors comprises: a first p-type vertical transistor and a second p-type vertical transistor each coupled with a positive voltage supply, and wherein the plurality of n-type vertical transistors comprises: a first n-type vertical transistor and a second n-type vertical transistor each coupled with a negative voltage supply. ### Claim 3 (depends on 2) The apparatus of claim 2, further comprising: a first conductive line that couples a gate terminal of the first p-type vertical transistor with a gate terminal of the first n-type vertical transistor; and a second conductive line that couples a gate terminal of the second p-type vertical transistor with a gate terminal of the second n-type vertical transistor. ### Claim 4 (depends on 2) The apparatus of claim 2, further comprising: a first conductive line that couples a source terminal of the first n-type vertical transistor with a drain terminal of the first p-type vertical transistor; and a second conductive line that couples a source terminal of the second n-type vertical transistor with a drain terminal of the second p-type vertical transistor. ### Claim 5 (depends on 2) The apparatus of claim 2, further comprising: a first conductive line that couples a source terminal of the first n-type vertical transistor and a drain terminal of the first p-type vertical transistor with a gate terminal of the second n-type vertical transistor and a gate terminal of the second p-type vertical transistor; and a second conductive line that couples a source terminal of the second n-type vertical transistor and a drain terminal of the second p-type vertical transistor with a gate terminal of the first n-type vertical transistor and a gate terminal of the first p-type vertical transistor. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising: a set of transistors disposed on the substrate and configured to selectively couple the latch with the fuse. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the memory array comprises memory cells that are positioned above a first region of the substrate, and wherein the latch is positioned above a second region of the substrate. ### Claim 8 (depends on 7) The apparatus of claim 7, further comprising: logic disposed on the second region of the substrate and configured for operating the memory array. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the memory array comprises a dynamic random access memory (DRAM) array. ### Claim 10 An apparatus, comprising: a substrate; a memory array coupled with the substrate; a latch configured to store information from a fuse for the memory array, the latch comprising a plurality of p-type vertical transistors and a plurality of n-type vertical transistors each at least partially disposed within an additional substrate above the substrate; a first plurality of conductive lines, wherein each conductive line in the first plurality of conductive lines couples source terminals of a respective set of the plurality of p-type vertical transistors that are connected in parallel; and a second plurality of conductive lines, wherein each conductive line in the second plurality of conductive lines couples drain terminals of a respective set of the plurality of n-type vertical transistors that are connective in parallel. ### Claim 11 An apparatus, comprising: a memory array coupled with a substrate; a fuse for the memory array; and a latch at least partially within an additional substrate above the substrate and configured to store information from the fuse, the latch comprising: a first p-type vertical transistor comprising a gate terminal and a drain terminal; a first n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the first p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the first p-type vertical transistor; a second p-type vertical transistor comprising a gate terminal and a drain terminal; and a second n-type vertical transistor comprising: a gate terminal coupled with the gate terminal of the second p-type vertical transistor, coupled with the drain terminal of the first p-type vertical transistor, and coupled with the source terminal of the first n-type vertical transistor; and a source terminal coupled with the drain terminal of the second p-type vertical transistor. ### Claim 12 (depends on 11) The apparatus of claim 11, further comprising: a first conductive line that couples the source terminal of the first n-type vertical transistor and the drain terminal of the first p-type vertical transistor with the gate terminal of the second n-type vertical transistor and the gate terminal of the second p-type vertical transistor; and a second conductive line that couples the source terminal of the second n-type vertical transistor and the drain terminal of the second p-type vertical transistor with the gate terminal of the first n-type vertical transistor and the gate terminal of the first p-type vertical transistor. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein the memory array is disposed at least partially within a first region of the substrate, and wherein the latch is above a second region of the substrate. ### Claim 14 An apparatus, comprising: a memory array coupled with a substrate; a fuse for the memory array; a latch at least partially within an additional substrate above the substrate and configured to store information from the fuse, the latch comprising: a first p-type vertical transistor comprising a gate terminal and a drain terminal; a first n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the first p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the first p-type vertical transistor; a second p-type vertical transistor comprising a gate terminal and a drain terminal; a second n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the second p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the second p-type vertical transistor; and a network of conductive lines that couples the first p-type vertical transistor, the first n-type vertical transistor, the second p-type vertical transistor, and the second n-type vertical transistor, wherein the network of conductive lines extends through the additional substrate in a three-dimensional manner; and a set of transistors coupled with the substrate and configured to selectively couple the fuse with respective gate terminals of the first p-type vertical transistor and the first n-type vertical transistor. ### Claim 15 An apparatus, comprising: a memory array coupled with a substrate; a fuse for the memory array; a latch at least partially within an additional substrate above the substrate and configured to store information from the fuse, the latch comprising: a first p-type vertical transistor comprising a gate terminal and a drain terminal; a first n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the first p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the first p-type vertical transistor; a second p-type vertical transistor comprising a gate terminal and a drain terminal; and a second n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the second p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the second p-type vertical transistor; a first negative voltage supply coupled with a drain terminal of the first n-type vertical transistor and second negative voltage supply coupled with a drain terminal of the second n-type vertical transistor; and a first positive voltage supply coupled with a source terminal of the first p-type vertical transistor and second positive voltage supply coupled with a source terminal of the second p-type vertical transistor. ### Claim 16 An apparatus, comprising: a first substrate; a memory array coupled with and disposed at least partially above the first substrate; a first p-type vertical transistor of a latch that is configured to store information from a fuse for the memory array, the first p-type vertical transistor at least partially within a second substrate that is above the first substrate; a first n-type vertical transistor of the latch, the first n-type vertical transistor at least partially within the second substrate that is above the first substrate; and a second n-type vertical transistor comprising a gate terminal coupled with a drain terminal of the first p-type vertical transistor and coupled with a source terminal of the first n-type vertical transistor. ### Claim 17 (depends on 16) The apparatus of claim 16, further comprising: a first conductive line that couples a gate terminal of the first p-type vertical transistor with a gate terminal of the first n-type vertical transistor; and a second conductive line that couples a drain terminal of the first p-type vertical transistor with a source terminal of the first n-type vertical transistor. ### Claim 18 (depends on 17) The apparatus of claim 17, further comprising: a second p-type vertical transistor of the latch, the second p-type vertical transistor at least partially within the second substrate that is above the first substrate; and a second n-type vertical transistor of the latch, the second n-type vertical transistor at least partially within the second substrate that is above the first substrate. ### Claim 19 (depends on 18) The apparatus of claim 18, further comprising: a third conductive line that couples a gate terminal of the second p-type vertical transistor with a gate terminal of the second n-type vertical transistor; and a fourth conductive line that couples a drain terminal of the second p-type vertical transistor with a source terminal of the second n-type vertical transistor.