# US 12,113,014 B2 · Integrated circuit including supervia and method of making

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- Number: US 12,113,014 B2
- Document ID: US12113014B2
- Status: Granted
- Kind: B2
- Application number: 18/356,354
- Filed: 2023-07-21
- Published: 2024-01-18
- Granted: 2024-10-08
- Earliest claimed: 2018-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kam-Tou Sio; Wei-Cheng Lin; Jiann-Tyng Tzeng
- Web page: https://patentgrep.com/patent/US12113014B2

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/421: {Skip vias, i.e. vias that do not connect all metallization layers that they pass through}
- H10W 20/427: {Power or ground buses}
- H10W 20/43: Layouts of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a substrate; and a first conductive line extending parallel to a top surface of the substrate. The first conductive line is a first distance from the substrate. The integrated circuit further includes a second conductive line extending parallel to the top surface of the substrate. The second conductive line is a second distance from the substrate. The integrated circuit further includes a third conductive line extending parallel to the top surface of the substrate. The third conductive line is a third distance from the substrate. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line, wherein a first angle between a sidewall of a lower portion of the supervia and the substrate is different from a second angle between a sidewall of an upper portion of the supervia and the substrate.

## Claims

### Claim 1

An integrated circuit comprising:
a substrate;
a first conductive line extending parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate;
a second conductive line extending parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is different from the first distance;
a third conductive line extending parallel to the top surface of the substrate, wherein the third conductive line is a third distance from the top surface of the substrate, and the third distance is different from the second distance and the first distance; and
a supervia directly connected to the first conductive line and the third conductive line, wherein a first angle between a lower sidewall of a lower portion of the supervia and the top surface of the substrate is different from a second angle between an upper sidewall of an upper portion of the supervia and the top surface of the substrate.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the second distance is less than the third distance, and the second distance is greater than the first distance.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, further comprising a first dielectric material surrounding the lower portion of the supervia.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, further comprising a second dielectric material surrounding the upper portion of the supervia.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, further comprising a fourth conductive line extending parallel to the top surface of the substrate, wherein the fourth conductive line is between the first conductive line and the substrate.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the first conductive line extends parallel to the third conductive line.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein the first conductive line extends perpendicular to the second conductive line.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, further comprising:
a fourth conductive line extending parallel to the top surface of the substrate; and
a second supervia directly connecting the second conductive line and the fourth conductive line.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the third conductive line is closer to the substrate than the fourth conductive line.

### Claim 10

An integrated circuit comprising:
a first conductive line;
a first dielectric layer over the first conductive line;
a second dielectric layer over the first dielectric layer;
a second conductive line in the second dielectric layer; and
a supervia directly connected to the first conductive line and the second conductive line, wherein the supervia has a varied tapered profile.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the supervia comprises a first portion in the first dielectric layer; and a second portion in the second dielectric layer.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein a first angle of a sidewall of the first portion relative to a top surface of the first conductive line is different from a second angle of a sidewall of the second portion relative to the top surface of the first conductive line.

### Claim 13 (depends on 10)

The integrated circuit of claim 10, further comprising a third conductive line and a fourth conductive line, wherein the supervia is between the third conductive line and the fourth conductive line.

### Claim 14 (depends on 10)

The integrated circuit of claim 10, further comprising:
a third conductive line; and
a via, wherein the via directly connects the first conductive line and the third conductive line.

### Claim 15

A method comprising:
depositing a first dielectric layer over a first conductive line;
forming a second conductive line;
depositing a second dielectric layer over the first dielectric layer;
forming a second conductive material to define a third conductive line;
forming a supervia opening in the first dielectric layer and the second dielectric layer, wherein the opening in the first dielectric layer has a different sidewall angle in comparison with the opening in the second dielectric layer; and
filling the supervia opening with a third conductive material to define a supervia, wherein the supervia directly connects to the first conductive line and the third conductive line.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the super via opening comprises forming the opening in the first dielectric layer simultaneously with forming the opening in the second dielectric layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein forming the supervia opening comprises forming the opening in the first dielectric layer prior to depositing the second dielectric layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein filling the supervia opening comprises filling the opening in the first dielectric layer prior to depositing the second dielectric layer.

### Claim 19 (depends on 15)

The method of claim 15, wherein filling the supervia opening comprises filling the opening in the second dielectric layer simultaneously with forming the second conductive material.

### Claim 20 (depends on 15)

The method of claim 15, wherein forming the second conductive line comprises forming the second conductive line in the first dielectric layer.