# US 12,113,012 B2 · Device, method and system to prevent pattern collapse in a semiconductor structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,012 B2 - Document ID: US12113012B2 - Status: Granted - Kind: B2 - Application number: 17/110,007 - Filed: 2020-12-02 - Published: 2022-06-02 - Granted: 2024-10-08 - Earliest claimed: 2020-12-02 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Errol Todd Ryan - Web page: https://patentgrep.com/patent/US12113012B2 ## CPC - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10W 20/42: Vias, e.g. via plugs - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/20: Multistable switching devices, e.g. memristors - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/801: {Constructional details of multistable switching devices} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10W 20/032: {of conductive barrier, adhesion or liner layers} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G11C: STATIC STORES (semiconductor memory devices H10B) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A semiconductor fabrication method, a semiconductor device and a semiconductor module. The method comprises: providing a stack on a substrate, the stack including a plurality of device layers comprising electrically conductive layers; patterning the stack using an etch to form trenches extending therethrough and pillars between the trenches; providing a carbon-containing liner on sidewalls of the trenches; wet cleaning and drying the stack after providing the carbon-containing liner; filling spaces between the pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form the semiconductor device. The carbon-containing liner may include a carbon-doped liner, such as a carbon-doped oxide liner provided by way of atomic layer deposition of an oxide at temperatures between about 100 degrees Celsius to about 300 degree Celsius using carbon as a precursor. ## Claims ### Claim 1 A semiconductor device comprising: a multilayered semiconductor structure including a substrate, a plurality of device layers on the substrate defining trenches extending therethrough and pillars between the trenches, one or more materials filling the trenches, and a carbon-containing liner along sidewalls of the trenches and disposed between the pillars and the one or more materials filling the trenches, one or more of the plurality of device layers including electrically conductive layers, wherein the sidewalls define a stepped configuration in a depthwise direction of the trenches, and wherein the carbon-containing liner includes a first carbon containing liner portion extending along the sidewalls and ending at a first step of the stepped configuration, and a second carbon containing liner portion extending along the sidewalls and ending at a second step of the stepped configuration; and electrical contact lines electrically coupled to the one or more of the plurality of device layers. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the carbon-containing liner includes at least one of a carbon-doped oxide liner or a carbon-doped nitride liner. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the carbon-containing liner includes a carbon-doped nitride liner, and wherein the sidewalls of the trenches having the carbon-doped nitride liner thereon do not include an oxide liner thereon. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the carbon-containing liner includes at least one of SiOC, SiCN or SiC. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the carbon-containing liner includes a nitride liner and a carbon-doped oxide liner on the nitride liner such that the nitride liner is between the pillars and the carbon-doped oxide liner. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein: the semiconductor device is a non-volatile memory device; and the pillars include memory cells of the non-volatile memory device, the memory cells defined in part by the plurality of device layers. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the carbon-containing liner includes a liner made of a material containing, in terms of atomic percentages, from about 10% to about 50% carbon. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the carbon-containing liner includes a liner made of a material that is one of substantially uniformly doped throughout its thickness, or non-uniformly doped throughout its thickness. ### Claim 9 A method of forming a semiconductor device including: providing a stack on a substrate, the stack including a plurality of device layers comprising electrically conductive layers; patterning the stack using a first etch to form first trenches extending therethrough and first pillars between the trenches; providing a first carbon-containing liner on sidewalls of the first trenches; wet cleaning and drying the stack after providing the first carbon-containing liner; patterning the stack, after wet cleaning and drying the stack, using a second etch to deepen the first trenches and lengthen the first pillars to form second trenches extending through the stack and second pillars between the second trenches; providing a second carbon-containing liner on sidewalls of the second trenches; wet cleaning and drying the stack after providing the second carbon-containing liner; filling spaces between the first pillars and the second pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form the semiconductor device. ### Claim 10 (depends on 9) The method of claim 9, wherein providing individual ones of the first carbon-containing liner and the second carbon-containing liner includes providing a carbon-doped liner at a temperature between about 100 degrees Celsius and about 300 degrees Celsius. ### Claim 11 (depends on 9) The method of claim 9, wherein providing individual ones of the first carbon-containing liner and the second carbon-containing liner includes using atomic layer deposition of a material of said individual ones of the first carbon-containing liner and the second carbon-containing liner together with a carbon precursor. ### Claim 12 (depends on 9) The method of claim 9, wherein individual ones of the first carbon-containing liner and the second carbon-containing liner include a nitride liner and a carbon-doped oxide liner on the nitride liner such that the nitride liner is between, on one hand, a corresponding one of the first pillars or the second pillars, and on another hand, the carbon-doped oxide liner. ### Claim 13 (depends on 9) The method of claim 9, wherein: the semiconductor device a non-volatile memory device; and the first pillars and the second pillars together include memory cells of the non-volatile memory device, the memory cells defined in part by the plurality of device layers. ### Claim 14 (depends on 9) The method of claim 9, wherein the carbon-containing liner includes a liner made of a material containing, in terms of atomic percentages, from about 10% to about 50% carbon. ### Claim 15 A semiconductor module comprising: input/output (I/O) circuitry to couple the semiconductor module with an external controller; one or more dies, each of the dies including: a multilayered semiconductor structure including a substrate, a plurality of device layers on the substrate defining trenches extending therethrough and pillars between the trenches, one or more materials filling the trenches, and a carbon-containing liner along sidewalls of the trenches and disposed between the pillars and the one or more materials filling the trenches, one or more of the plurality of device layers including electrically conductive layers, wherein the sidewalls define a stepped configuration in a depthwise direction of the trenches, and wherein the carbon-containing liner includes a first carbon containing liner portion extending along the sidewalls and ending at a first step of the stepped configuration, and a second carbon containing liner portion extending along the sidewalls and ending at a second step of the stepped configuration; and electrical contact lines electrically coupled to the one or more of the plurality of device layers. ### Claim 16 (depends on 15) The semiconductor module of claim 15, wherein: the semiconductor module is a memory module; each of the dies is a non-volatile memory device; and the pillars include memory cells of the non-volatile memory device, the memory cells defined in part by the plurality of device layers. ### Claim 17 (depends on 15) The semiconductor module of claim 15, wherein the carbon-containing liner includes at least one of a carbon-doped oxide liner or a carbon-doped nitride liner. ### Claim 18 (depends on 15) The semiconductor module of claim 15, wherein the carbon-containing liner includes at least one of SiOC, SiCN or SiC.