# US 12,113,006 B2 · Semiconductor package

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- Number: US 12,113,006 B2
- Document ID: US12113006B2
- Status: Granted
- Kind: B2
- Application number: 18/080,683
- Filed: 2022-12-13
- Published: 2023-04-13
- Granted: 2024-10-08
- Earliest claimed: 2021-03-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chin-Hua Wang; Shu-Shen Yeh; Yu-Sheng Lin; Po-Yao Lin; Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US12113006B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/65: Shapes or dispositions of interconnections
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/685: comprising multiple insulating layers
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7428: {used to support diced chips prior to mounting}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 40/10: Arrangements for heating
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/251: {Organics}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/327: {Multiple die-attach connectors having different sizes}
- H10W 72/348: {Top-view layouts, e.g. mirror arrays}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.

## Claims

### Claim 1

A semiconductor package, comprising:
an interposer;
a semiconductor die disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface;
an underfill layer disposed between the front surface of the semiconductor die and the interposer; and
an encapsulant laterally encapsulating the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die, and a side of the at least one side surface is at the same level height as a top surface of the encapsulant.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein a first offset of the chamfered corner along a first direction parallel to the first side surface is greater than or equal to about 5 micrometers and less than or equal to a half of a first length of the semiconductor die, and a second offset of the chamfered corner along a second direction parallel to the second side surface is greater than or equal to about 5 micrometers and less than or equal to a half of a second length of the semiconductor die.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the at least one side surface of the chamfered corner comprises a third side surface and a fourth side surface, the third side surface extends between the first side surface and the fourth side surface, the fourth side surface extends between the third side surface and the second side surface, an exterior angle between the third side surface and the first side surface is greater than 0 degree and less than about 90 degree, and an exterior angle between the fourth side surface and a virtual plane paralleled with the first side surface is greater than 0 degree and less than about 90 degree.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein the exterior angle between the third side surface and the first side surface is the same as the exterior angle between the fourth side surface and the virtual plane paralleled with the first side surface.

### Claim 5 (depends on 3)

The semiconductor package of claim 3, wherein the exterior angle between the third side surface and the first side surface is different from the exterior angle between the fourth side surface and the virtual plane paralleled with the first side surface.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the at least one side surface of the chamfered corner comprises a third side surface and a fourth side surface, the third side surface connects the first side surface and the fourth side surface, at least one of an exterior angle between the first side surface and the third side surface and an exterior angle between the fourth side surface and the second side surface is about 90 degree, and both of the third side surface and the fourth side surface are connected with the back surface.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the at least one side surface of the chamfered corner comprises a curved side surface.

### Claim 8 (depends on 6)

The semiconductor package of claim 6, wherein the curved side surface has a concave profile or a convex profile.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the underfill layer is in contact with the at least one side surface of the chamfered corner.

### Claim 10

A semiconductor package, comprising:
an interposer;
semiconductor dies disposed over and electrically connected with the interposer, wherein each of the semiconductor dies has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and at least one semiconductor die of the semiconductor dies comprises a chamfered outer corner connected with the back surface, the first side surface and the second side surface, the first side surface and the second side surface of the at least one semiconductor die do not face toward other semiconductor dies, the chamfered outer corner comprises at least one side surface;
a first underfill layer disposed between the semiconductor dies and between the semiconductor dies and the interposer; and
an encapsulant laterally encapsulating the semiconductor dies and the first underfill layer, and a side of the at least one side surface is at the same level height as a top surface of the encapsulant.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein a first offset of the chamfered corner along a first direction parallel to the first side surface is greater than or equal to about 5 micrometers and less than or equal to a half of a first length of the at least one semiconductor die, and a second offset of the chamfered corner along a second direction parallel to the second side surface is greater than or equal to about 5 micrometers and less than or equal to a half of a second length of the at least one semiconductor die.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, further comprising:
a circuit substrate;
first conductive terminals disposed on and electrically connected to the circuit substrate;
second conductive terminals disposed on and electrically connected to the circuit substrate, wherein the interposer is electrically connected to the circuit substrate through the first conductive terminals, and the first conductive terminals and the second conductive terminals are disposed on opposite sides of the circuit substrate; and
a second underfill layer disposed between the interposer and the circuit substrate, wherein the second underfill layer encapsulates the first conductive terminals.

### Claim 13 (depends on 10)

The semiconductor package of claim 10, further comprising:
a stiffener ring disposed on the circuit substrate to surround the semiconductor dies.

### Claim 14 (depends on 13)

The semiconductor package of claim 13, further comprising:
a lid layer, adhered on the stiffener ring and overlying the semiconductor dies; and
a thermal interface material (TIM) layer at least disposed between the semiconductor dies and the lid layer.

### Claim 15 (depends on 10)

The semiconductor package of claim 10, wherein the at least one side surface of the chamfered outer corner comprises a third side surface and a fourth side surface, the third side surface connects the first side surface and the fourth side surface, and an obtuse angle is included between the third side surface and the fourth side surface, and both the third side surface and the fourth side surface are connected with the back surface.

### Claim 16 (depends on 10)

The semiconductor package of claim 10, wherein the at least one side surface of the chamfered outer corner comprises a third side surface and a fourth side surface, the third side surface connects the first side surface and the fourth side surface, and a right angle is included between the third side surface and the fourth side surface.

### Claim 17 (depends on 10)

The semiconductor package of claim 10, wherein the at least one side surface of the chamfered corner comprises a curved side surface.

### Claim 18

A semiconductor package, comprising:
an interposer;
a first semiconductor die disposed over and electrically connected with the interposer, wherein the first semiconductor die has a front surface, a back surface, a first side surface, a second side surface and a third side surface, the back surface is opposite to the front surface, the first side surface, the second side surface and the third side surface are connected with the front surface and the back surface, the first semiconductor die comprises a first chamfered corner and a first corner, the first chamfered corner is connected with the back surface, the first side surface and the second side surface, and the first corner is connected with the first side surface and the third side surface;
a second semiconductor die disposed aside the first semiconductor die and electrically connected with the interposer, wherein the second semiconductor die has a fourth side surface, a fifth side surface and a sixth side surface, the second semiconductor die comprises a second chamfered corner and a second corner, the second chamfered corner is connected with the fourth side surface and the fifth side surface, the second corner is connected with the fourth side surface and the sixth side surface, and the sixth side surface faces toward the third side surface;
an underfill layer disposed between the first semiconductor die and the second semiconductor die, between the first semiconductor die and the interposer, and between the second semiconductor die and the interposer; and
an encapsulant laterally encapsulating the first semiconductor die, the second semiconductor die and the underfill layer, wherein the encapsulant is in contact with the first chamfered corner and the second chamfered corner, and a side of the first chamfered corner is at the same level height as a top surface of the encapsulant.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, wherein a right angle is included between the first side surface and the third side surface and between the fourth side surface and the sixth side surface.

### Claim 20 (depends on 18)

The semiconductor package of claim 18, wherein the underfill layer is in contact with the first chamfered corner and the second chamfered corner.