# US 12,113,004 B2 · Electronic package and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,004 B2 - Document ID: US12113004B2 - Status: Granted - Kind: B2 - Application number: 17/674,457 - Filed: 2022-02-17 - Published: 2023-06-22 - Granted: 2024-10-08 - Earliest claimed: 2021-12-21 - Assignees: Siliconware Precision Industries Co., Ltd. - Applicants: Siliconware Precision Industries Co., Ltd. - Inventors: Chung-Yu Ke; Po-Kai Huang; Liang-Pin Chen - Web page: https://patentgrep.com/patent/US12113004B2 ## CPC - H10W 70/685: comprising multiple insulating layers - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/74: {using temporarily an auxiliary support} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/7428: {used to support diced chips prior to mounting} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/072: {of bump connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 90/00: Package configurations - H10W 90/722: {between stacked chips} - H10W 90/732: {between stacked chips} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract An electronic package is provided and includes stacking a first packaging module having a circuit structure, an electronic element, a plurality of first conductive elements and a first packaging layer with a second packaging module having a routing structure, a plurality of second conductive elements and a second packaging layer, so that the second packaging layer is formed on the first packaging layer in a manner that the routing structure is overlapped on the circuit structure, where each of the second conductive elements is correspondingly bonded with each of the first conductive elements. Accordingly, the circuit structure and the routing structure are manufactured separately at the same time, so as to shorten the process time and control the stress distribution on the circuit structure and the routing structure separately. ## Claims ### Claim 1 An electronic package, comprising: a circuit structure; an electronic element disposed on and electrically connected to the circuit structure; a plurality of first conductive elements disposed on and electrically connected to the circuit structure; a first packaging layer formed on the circuit structure to cover the electronic element and the plurality of conductive elements; and a packaging module disposed on the first packaging layer, wherein the packaging module includes a routing structure, a plurality of second conductive elements disposed on and electrically connected to the routing structure, and a second packaging layer formed on the routing structure to cover the plurality of second conductive elements, wherein the packaging module is disposed on the first packaging layer via the second packaging layer thereof, such that the routing structure is overlapped on the circuit structure, and wherein each of the second conductive elements is correspondingly and directly bonded with and electrically connected to each of the first conductive elements. ### Claim 2 (depends on 1) The electronic package of claim 1, wherein the first packaging layer has a coefficient of thermal expansion different from a coefficient of thermal expansion of the second packaging layer. ### Claim 3 (depends on 1) The electronic package of claim 1, further comprising a bonding layer formed on the first packaging layer for the second packaging layer to be attached to the first packaging layer via the bonding layer. ### Claim 4 (depends on 3) The electronic package of claim 3, wherein the bonding layer covers joints between the plurality of first conductive elements and the plurality of second conductive elements. ### Claim 5 (depends on 1) The electronic package of claim 1, wherein end portions of the plurality of first conductive elements and end portions of the plurality of second conductive elements are exposed from the first packaging layer and the second packaging layer, respectively. ### Claim 6 A method of manufacturing an electronic package, comprising: disposing at least an electronic element and a plurality of first conductive elements on a circuit structure, wherein the circuit structure is electrically connected to the electronic element and the plurality of first conductive elements; forming a first packaging layer on the circuit structure, wherein the first packaging layer covers the electronic element and the plurality of first conductive elements to form a first packaging module; and disposing a second packaging module on the first packaging layer of the first packaging module, wherein the second packaging module comprises a routing structure, a plurality of second conductive elements disposed on the routing structure and a second packaging layer formed on the routing structure to cover the plurality of second conductive elements, and wherein the routing structure is overlapped on the circuit structure, each of the second conductive elements is correspondingly and directly bonded with and electrically connected to each of the first conductive elements, and the second packaging module is disposed on the first packaging layer of the first packaging module via the second packaging layer. ### Claim 7 (depends on 6) The method of claim 6, wherein the first packaging layer has a coefficient of thermal expansion different from a coefficient of thermal expansion of the second packaging layer. ### Claim 8 (depends on 6) The method of claim 6, further comprising forming a bonding layer on the first packaging layer for the second packaging layer to be disposed on the first packaging layer via the bonding layer. ### Claim 9 (depends on 8) The method of claim 8, wherein the bonding layer covers joints between the plurality of first conductive elements and the plurality of second conductive elements. ### Claim 10 (depends on 6) The method of claim 6, wherein end portions of the plurality of first conductive elements and end portions of the plurality of second conductive elements are exposed from the first packaging layer and the second packaging layer, respectively.