# US 12,113,003 B2 · Semiconductor device with composite middle interconnectors

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- Number: US 12,113,003 B2
- Document ID: US12113003B2
- Status: Granted
- Kind: B2
- Application number: 18/217,721
- Filed: 2023-07-03
- Published: 2023-11-09
- Granted: 2024-10-08
- Earliest claimed: 2021-12-23
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Pei Cheng Fan
- Web page: https://patentgrep.com/patent/US12113003B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 72/07253: {changes in shapes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/30: Die-attach connectors
- H10W 72/931: {Shapes of bond pads}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a package structure comprising a first side and a second side opposite to the first side;
an interposer structure positioned over the first side of the package structure;
a first die positioned over the interposer structure;
a second die positioned over the interposer structure; and
a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively comprising:
a bottom exterior layer positioned on the second side of the package structure;
a bottom interior layer enclosed by the bottom exterior layer;
a cavity enclosed by the bottom interior layer;
a base structure positioned opposite to the first side of the package structure and electrically connected to the plurality of bottom interconnectors; and
a bottom underfill layer positioned between the package structure and the base structure, and surrounding the plurality of bottom interconnectors.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a plurality of through package vias positioned along the package structure, wherein the plurality of middle interconnectors and the plurality of bottom interconnectors are electrically coupled through the plurality of through package vias.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first die is configured as a logic die and the second die is configured as a memory die.

### Claim 4

A semiconductor device, comprising:
a package structure comprising a first side and a second side opposite to the first side;
an interposer structure positioned over the first side of the package structure;
a first die positioned over the interposer structure;
a second die positioned over the interposer structure; and
a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively comprising:
a bottom exterior layer positioned on the second side of the package structure;
a bottom interior layer enclosed by the bottom exterior layer;
a cavity enclosed by the bottom interior layer;
a base structure positioned opposite to the first side of the package structure and electrically connected to the plurality of bottom interconnectors; and
an upper circular pad and a lower circular pad;
wherein the upper circular pad is positioned between the bottom exterior layer and the package structure;
wherein the lower circular pad is positioned between the bottom exterior layer and the base structure.