# US 12,112,998 B2 · Semiconductor device and method for forming the same

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- Number: US 12,112,998 B2
- Document ID: US12112998B2
- Status: Granted
- Kind: B2
- Application number: 18/343,399
- Filed: 2023-06-28
- Published: 2023-10-26
- Granted: 2024-10-08
- Earliest claimed: 2020-07-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Marcus Johannes Henricus Van Dal; Gerben Doornbos
- Web page: https://patentgrep.com/patent/US12112998B2

## CPC

- H10D 84/0158: {the components including FinFETs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a semiconductor fin, a source/drain structure, a first buried power line, a contact, a first through substrate via (TSV), and a second TSV. The substrate has a well region extending a front-side surface of the substrate into the substrate. The semiconductor fin is on the well region. The source/drain structure is on the semiconductor fin. The first buried power line is electrically coupled to the source/drain structure on the first semiconductor fin. The first buried power line has a length extending along a lengthwise direction of the first semiconductor fin and a height extending within the well region. The first TSV extends from a back-side surface of the substrate through the substrate to the first buried power line. The second TSV extends from the back-side surface of the substrate to the well region.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a well region extending from a front-side surface of the substrate into the substrate;
a first semiconductor fin on the well region;
a shallow trench isolation (STI) structure laterally surrounding a portion of the first semiconductor fin;
a source/drain structure on the first semiconductor fin;
a first buried power line electrically coupled to the source/drain structure on the first semiconductor fin, the first buried power line having a length extending along a lengthwise direction of the first semiconductor fin and a height extending from within the STI structure to within the well region;
a first through substrate via (TSV) extending from a back-side surface of the substrate to the first buried power line; and
a second TSV extending from the back-side surface of the substrate to the well region, wherein a front-side surface of the second TSV exposes in the well region to form an interface with the well region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein in a plan view, the second TSV is between the first semiconductor fin and the first buried power line.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a second semiconductor fin on the well region, wherein in a plan view, the second TSV is between the first and second semiconductor fins.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising a second buried power line having a length extending along the lengthwise direction of the first semiconductor fin, wherein the first semiconductor fin is between the second buried power line and the first buried power line.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein in a plan view, the second TSV non-overlaps the first semiconductor fin.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a gate structure extending across the first semiconductor fin, wherein in a plan view, the second TSV overlaps the gate structure.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second TSV has substantially the same depth as the first TSV.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein an interface formed by the first TSV and the first buried power line is substantially level with an interface formed by the well region and the second TSV.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the well region is an N-type well region.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the well region is a P-type well region.

### Claim 11

A semiconductor device, comprising:
a substrate having a P-type well region and an N-type well region adjacent to the P-type well region, wherein the P-type well region and the N-type well region extend from a front-side surface of the substrate into the substrate;
a first semiconductor fin upwardly extending from the P-type well region in a vertical direction;
a second semiconductor fin upwardly extending from the N-type well region in the vertical direction;
a first through substrate via (TSV) extending from a back-side surface of the substrate to the P-type well region, wherein the first TSV overlaps the first semiconductor fin in the vertical direction; and
a second TSV extending from the back-side surface of the substrate to the N-type well region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising:
a third semiconductor fin on the substrate;
a source/drain structure on the third semiconductor fin;
a buried power line partially embedded in the substrate;
a source/drain contact electrically connecting the source/drain structure to the buried power line; and
a third TSV extending from the back-side surface of the substrate to the buried power line.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, further comprising:
a third semiconductor fin over the substrate;
first and second source/drain structures respectively on the first and third semiconductor fins;
a multilayer interconnect stack over the first and second source/drain structures; and
a third TSV extending from the back-side surface of the substrate to the multilayer interconnect stack.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, further comprising a doping layer between the first TSV and the P-type well region and doped with a p-type dopant.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein a front-side surface of the second TSV forms an interface with the N-type well region.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, further comprising a metal silicide layer between the first TSV and the P-type well region.

### Claim 17

A semiconductor device, comprising:
a semiconductive substrate having a well region extending from a front-side surface of the semiconductive substrate into the semiconductive substrate;
a first fin on the well region;
a second fin on the well region;
a gate across the first and second fins;
first source/drain features on the first fin and at opposite sides of the gate;
second source/drain features on the second fin and at opposite sides of the gate; and
a first through substrate via (TSV) extending from a back-side of the semiconductive substrate to the well region, wherein from a top view, the first TSV is between the first and second fins, and an entirety of a front-side surface of the first TSV forms an interface with the well region.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a buried power rail having a first portion in the well region and a second portion exposed from the front-side surface of the semiconductive substrate, wherein the buried power rail is electrically connected to one of the first source/drain features, wherein the first TSV non-overlaps the buried power rail from the top view.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further comprising:
a second TSV extending from the back-side of the semiconductive substrate to the buried power rail.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein the first TSV overlaps the gate from the top view.