# US 12,112,997 B2 · Micro through-silicon via for transistor density scaling

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- Number: US 12,112,997 B2
- Document ID: US12112997B2
- Status: Granted
- Kind: B2
- Application number: 18/216,040
- Filed: 2023-06-29
- Published: 2023-11-09
- Granted: 2024-10-08
- Earliest claimed: 2018-07-31
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Bok Eng Cheah; Choong Kooi Chee; Jackson Chung Peng Kong; Wai Ling Lee; Tat Hin Tan
- Web page: https://patentgrep.com/patent/US12112997B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/01: {Manufacture or treatment}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10D 1/68: Capacitors having no potential barriers
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

## Claims

### Claim 1

An integrated circuit (IC) package, comprising:
a package substrate;
an IC die coupled to the package substrate, the IC die comprising:
a silicon substrate having an active device layer and a backside surface opposite the active device layer;
a plurality of metal layers above the active device layer, the plurality of metal layers comprising an uppermost metal layer, a second to uppermost metal layer below the uppermost layer, a third to uppermost metal layer below the second to uppermost metal layer, and a fourth to uppermost metal layer below the third to uppermost metal layer;
a through silicon via (TSV) extending through the silicon substrate, through the active device layer, and through the fourth to uppermost metal layer, the TSV having a top surface below the third to uppermost metal layer; and
a via between and in contact with the top surface of the TSV and an interconnect of the third to uppermost metal layer; and
a bump above an interconnect of the uppermost metal layer.

### Claim 2 (depends on 1)

The IC package of claim 1, wherein the TSV has a first width and a second width, the second width closer to the package substrate than the first width, and the second width greater than the first width.

### Claim 3 (depends on 1)

The IC package of claim 1, wherein the bump is a microbump.

### Claim 4 (depends on 1)

The IC package of claim 1, further comprising:
a second bump coupled to the TSV.

### Claim 5 (depends on 4)

The IC package of claim 4, wherein the second bump is a package bump.

### Claim 6 (depends on 1)

The IC package of claim 1, wherein the TSV has a first width where the TSV extends through the active device layer, and a second width in the silicon substrate, the second width different from the first width.

### Claim 7 (depends on 1)

The IC package of claim 1, further comprising:
a keep-out-region along sides of the TSV.

### Claim 8 (depends on 1)

The IC package of claim 1, wherein the TSV comprises copper.

### Claim 9

An integrated circuit (IC) package, comprising:
a package substrate;
a first die coupled to the package substrate, the first die comprising:
a silicon substrate having an active device layer and a backside surface opposite the active device layer, the active device layer closer to the package substrate than the backside surface;
a plurality of metal layers above the active device layer, the plurality of metal layers comprising an uppermost metal layer, a second to uppermost metal layer below the uppermost layer, a third to uppermost metal layer below the second to uppermost metal layer, and a fourth to uppermost metal layer below the third to uppermost metal layer;
a through silicon via (TSV) extending through the silicon substrate, through the active device layer, and through the fourth to uppermost metal layer, the TSV having a top surface below the third to uppermost metal layer; and
a via between and in contact with the top surface of the TSV and an interconnect of the third to uppermost metal layer;
a bump above an interconnect of the uppermost metal layer, the bump between the first die and the package substrate; and
a second die conductively coupled to the first die, wherein the first die is between the second die and the package substrate.

### Claim 10 (depends on 9)

The IC package of claim 9, further comprising:
a second bump coupled to the TSV.

### Claim 11 (depends on 9)

The IC package of claim 9, wherein the TSV has a first width where the TSV extends through the active device layer, and a second width in the silicon substrate, the second width different from the first width.

### Claim 12 (depends on 9)

The IC package of claim 9, further comprising:
a keep-out-region along sides of the TSV.

### Claim 13 (depends on 9)

The IC package of claim 9, wherein the TSV comprises copper.

### Claim 14

An integrated circuit (IC) package, comprising:
a package substrate;
a base die coupled to the package substrate without an intervening die between the base die and the package substrate, the base die comprising:
a silicon substrate having an active device layer and a backside surface opposite the active device layer;
a plurality of metal layers above the active device layer, the plurality of metal layers comprising an uppermost metal layer, a second to uppermost metal layer below the uppermost layer, a third to uppermost metal layer below the second to uppermost metal layer, and a fourth to uppermost metal layer below the third to uppermost metal layer;
a through silicon via (TSV) extending through the silicon substrate, through the active device layer, and through the fourth to uppermost metal layer, the TSV having a top surface below the third to uppermost metal layer; and
a via between and in contact with the top surface of the TSV and an interconnect of the third to uppermost metal layer;
a bump above an interconnect of the uppermost metal layer; and
a die conductively coupled to the base die, wherein the base die is between the die and the package substrate.

### Claim 15 (depends on 14)

The IC package of claim 14, wherein the TSV has a first width and a second width, the second width closer to the package substrate than the first width, and the second width greater than the first width.

### Claim 16 (depends on 14)

The IC package of claim 14, wherein the bump is a microbump.

### Claim 17 (depends on 14)

The IC package of claim 14, further comprising:
a second bump coupled to the TSV.

### Claim 18 (depends on 17)

The IC package of claim 17, wherein the second bump is a package bump.

### Claim 19 (depends on 14)

The IC package of claim 14, wherein the TSV has a first width where the TSV extends through the active device layer, and a second width in the silicon substrate, the second width different from the first width.

### Claim 20 (depends on 14)

The IC package of claim 14, further comprising:
a keep-out-region along sides of the TSV.