# US 12,112,996 B2 · Semiconductor device, imaging unit, and electronic apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,996 B2 - Document ID: US12112996B2 - Status: Granted - Kind: B2 - Application number: 18/046,387 - Filed: 2022-10-13 - Published: 2023-03-02 - Granted: 2024-10-08 - Earliest claimed: 2018-03-14 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Takahiro Kamei; Yoichi Ootsuka - Web page: https://patentgrep.com/patent/US12112996B2 ## CPC - H10F 39/811: {Interconnections} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H04N 25/70: SSIS architectures; Circuits associated therewith - H10F 39/018: {of hybrid image sensors} - H10F 39/809: {of hybrid image sensors} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias} - H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers} - H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 90/00: Package configurations - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract Provided is a semiconductor device having high planarity in an in-plane direction. This semiconductor device includes a semiconductor substrate, a first plating film pattern, a second plating film pattern, and an insulating layer. The semiconductor substrate has a first surface, and a second surface on a side opposite to the first surface. The first plating film pattern includes a first portion that covers a first regional portion of the first surface, and a second portion that is stacked to cover a portion of the first portion. The second plating film pattern includes a third portion that covers a second regional portion different from the first regional portion of the first surface, and also includes a fourth portion that is stacked to cover a portion of the third portion. A portion between the second portion and the fourth portion is filled with the insulating layer. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate that has a first surface and a second surface on a side opposite to the first surface; a first metal film pattern that includes a first portion and a second portion, wherein the first portion covers a first regional portion of the first surface, the second portion is stacked on the first portion, the second portion is smaller in area than the first portion in a plan view such that the second portion covers a portion of an upper surface of the first portion in the plan view, the upper surface of the first portion is parallel to the first surface of the semiconductor substrate, the second portion includes a third surface and a fourth surface on a side opposite to the third surface, and the third surface is substantially parallel to the fourth surface; a second metal film pattern that includes a third portion and a fourth portion, wherein the third portion covers a second regional portion of the first surface different from the first regional portion of the first surface, and the fourth portion is stacked on the third portion to cover a portion of the third portion; and an insulating layer between the second portion and the fourth portion. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein an upper surface of the second portion, an upper surface of the fourth portion, and an upper surface of the insulating layer are at substantially an equal height position in a thickness direction of the semiconductor device. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the first metal film pattern further includes a constituent material that is substantially identical to a constituent material of the second metal film pattern. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the first metal film pattern is electrically separated from the second metal film pattern. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the first portion in the first metal film pattern is integrated to the third portion in the second metal film pattern. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate further includes a first through hole from the first surface to the second surface, the first metal film pattern further includes a first through-hole portion on the first through hole, and the first through-hole portion is coupled to the first portion. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, further comprising a semiconductor element near the second surface of the semiconductor substrate, wherein the first through-hole portion is further coupled to the semiconductor element. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the semiconductor substrate further includes a second through hole from the first surface to the second surface, and the second metal film pattern further includes a second through-hole portion on the second through hole, and the second through-hole portion is coupled to the third portion. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, further comprising a ground terminal near the second surface of the semiconductor substrate, wherein the second through-hole portion is further coupled to the ground terminal. ### Claim 10 (depends on 6) The semiconductor device according to claim 6, further comprising: a plurality of first metal film patterns including the first metal film pattern; and a plurality of second metal film patterns between the plurality of first metal film patterns in an in-plane direction along the first surface, wherein the plurality of second metal film patterns includes the second metal film pattern. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the plurality of second plating film patterns includes a plurality of third portions coupled to each other, and the plurality of third portions includes the third portion. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the plurality of third portions is coupled to an external heat dissipating portion. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the first metal film pattern and the second metal film pattern each form an inverted T shape in a cross-section view. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the second portion partially overlaps the upper surface of the first portion in a thickness direction of the semiconductor device. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, further comprising a planarizing film that fills at least a portion between the second portion and the fourth portion. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein the planarizing film covers the insulating layer and fills a space between the first portion and the third portion. ### Claim 17 (depends on 15) The semiconductor device according to claim 15, wherein the planarizing film comprises an organic insulating material. ### Claim 18 An imaging unit, comprising: an imaging device; and a semiconductor device on which the imaging device is mounted, wherein the semiconductor device includes: a semiconductor substrate that has a first surface and a second surface on a side opposite to the first surface; a first metal film pattern that includes a first portion and a second portion, wherein the first portion covers a first regional portion of the first surface, the second portion is stacked on the first portion, the second portion is smaller in area than the first portion in a plan view such that the second portion covers a portion of an upper surface of the first portion in the plan view, the upper surface of the first portion is parallel to the first surface of the semiconductor substrate, the second portion includes a third surface and a fourth surface on a side opposite to the third surface, and the third surface is substantially parallel to the fourth surface; a second metal film pattern that includes a third portion and a fourth portion, wherein the third portion covers a second regional portion of the first surface different from the first regional portion of the first surface, and the fourth portion is stacked on the third portion to cover a portion of the third portion; and an insulating layer between the second portion and the fourth portion. ### Claim 19 An electronic apparatus, comprising: an imaging device; and a semiconductor device on which the imaging device is mounted, wherein the semiconductor device includes: a semiconductor substrate that has a first surface and a second surface on a side opposite to the first surface; a first metal film pattern that includes a first portion and a second portion, wherein the first portion covers a first regional portion of the first surface, the second portion is stacked on the first portion, the second portion is smaller in area than the first portion in a plan view such that the second portion covers a portion of an upper surface of the first portion in the plan view, the upper surface of the first portion is parallel to the first surface of the semiconductor substrate, the second portion includes a third surface and a fourth surface on a side opposite to the third surface, and the third surface is substantially parallel to the fourth surface; a second metal film pattern that includes a third portion and a fourth portion, wherein the third portion covers a second regional portion of the first surface different from the first regional portion of the first surface, and the fourth portion is stacked on the third portion to cover a portion of the third portion; and an insulating layer between the second portion and the fourth portion.