# US 12,112,995 B2 · Low capacitance through substrate via structures

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- Number: US 12,112,995 B2
- Document ID: US12112995B2
- Status: Granted
- Kind: B2
- Application number: 17/839,222
- Filed: 2022-06-13
- Published: 2022-09-29
- Granted: 2024-10-08
- Earliest claimed: 2016-03-07
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Deepak C. Pandey; Haitao Liu; Chandra Mouli
- Web page: https://patentgrep.com/patent/US12112995B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/2128: {Coaxial through-semiconductor vias}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4424: {Copper alloys}
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10W 44/212: {Coaxial feed-throughs in substrates}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

## Claims

### Claim 1

An apparatus, comprising:
an opening formed in a substrate, wherein the opening has at least one sidewall;
a first dielectric at least formed on the sidewall of the opening;
a first conductor at least formed on the first dielectric;
a second dielectric at least formed on the first conductor;
a second conductor at least formed on a sidewall of the second dielectric; and
a conductive coupling configured to short the first conductor to the substrate via a voltage reference node and extend across the first dielectric.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the voltage reference node is a ground node.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the voltage reference node is a substrate voltage node.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the first and second dielectrics are silicon dioxide.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein a first capacitance is formed from a combination of the substrate, the first dielectric and the first conductor, and wherein a second capacitance is formed from a combination of the first conductor, the second dielectric, and the second conductor.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein a capacitance value of the second dielectric is at or below a target TSV capacitance value.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the second dielectric has a thickness based on a desired capacitance value.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein each of the first dielectric, the second dielectric, and the first conductor are in a ring shape.

### Claim 9

An apparatus, comprising:
a substrate with a through substrate via formed in an opening therein, wherein the through substrate via comprises:
a first dielectric formed on a sidewall of the opening;
a second dielectric;
a first conductor disposed between the first and second dielectrics; and
a second conductor disposed on the second dielectric, wherein a conductive coupling extends across the first dielectric and couples the first conductor to a voltage reference in the substrate.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the substrate includes one or more circuits on a front side.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the first dielectric is an oxide.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the second dielectric is a low dielectric constant material.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the first conductor comprises tantalum, copper, polysilicon, silver, aluminum, or combinations thereof.

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein the second dielectric has a thickness based on a desired capacitance value, and wherein a capacitance formed from the first and second conductors and the second dielectric provides the desired capacitance value.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein the second conductor is floating.

### Claim 16 (depends on 9)

The apparatus of claim 9, wherein a thickness of the first conductor is 20 nm.

### Claim 17 (depends on 9)

The apparatus of claim 9, wherein a thickness of the first liner is 100 Å to 6000 Å.

### Claim 18

An apparatus comprising:
an opening formed in a substrate, wherein the opening has at least one sidewall;
a first layer formed on the sidewall of the opening;
a conductive layer formed on the first layer;
a second layer formed on the conductive layer, wherein the first layer, the conductive layer and the second layer are configured to fill a part of the opening; and
a conductor configured to fill a remaining part of the opening, wherein a conductive coupling extends above the first layer and couples the conductive layer to a voltage reference in the substrate.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the conductive layer comprises:
a barrier layer configured to cover the first layer; and
a seed layer configured to cover the barrier layer, wherein the second layer is formed on the seed layer.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the barrier layer comprises tantalum and the seed layer comprises copper.

### Claim 21

An apparatus comprising:
an opening in a substrate, wherein the opening has at least one sidewall;
a dielectric layer on the sidewall of the opening;
a conductive barrier layer comprising tantalum on the dielectric layer;
a conductive seed layer comprising copper on the conductive barrier layer, wherein the dielectric layer, the conductive barrier layer, and the conductive seed layer are configured to fill a part of the opening; and
a conductor configured to at least partially fill a remaining part of the opening.