# US 12,112,989 B2 · Semiconductor device with tunable epitaxy structures and method of forming the same

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- Number: US 12,112,989 B2
- Document ID: US12112989B2
- Status: Granted
- Kind: B2
- Application number: 17/815,085
- Filed: 2022-07-26
- Published: 2022-11-10
- Granted: 2024-10-08
- Earliest claimed: 2019-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Hao Lin; Tzu-Hsiang Hsu; Chong-De Lien; Szu-Chi Yang; Hsin-Wen Su; Chih-Hsiang Huang
- Web page: https://patentgrep.com/patent/US12112989B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10P 50/642: {Chemical etching}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

## Claims

### Claim 1

A device comprising:
a first fin and a second fin;
a first gate structure disposed on the first fin and a second gate structure disposed on the second fin;
a first source/drain feature extending within the first fin to a first depth, the first source/drain feature including a first epitaxial layer and a second epitaxial layer disposed on the first epitaxial layer; and
a second source/drain feature extending within the second fin to a second depth that is different than the first depth, the second source/drain feature including a third epitaxial layer and a fourth epitaxial layer disposed on the third epitaxial layer, wherein a first ratio of a height of the first epitaxial layer to the first depth of the first source/drain is greater than a second ratio of a height of the third epitaxial layer to the second depth of the second source/drain feature, wherein the second depth is greater than the first depth.

### Claim 2 (depends on 1)

The device of claim 1, wherein a third ratio of a height of the second epitaxial layer to the first depth of the first source/drain is less than a fourth ratio of a height of the fourth epitaxial layer to the second depth of the second source/drain feature.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first source/drain feature includes a p-type dopant and the second source/drain feature includes an n-type dopant.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second source/drain feature is wider than the first source/drain feature.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first epitaxial layer includes a first concentration of germanium and the second epitaxial layer includes a second concentration of germanium that is different than the first concentration of germanium.

### Claim 6 (depends on 5)

The device of claim 5, wherein first concentration of germanium is less than 30% and the second concentration of germanium is greater than 30%.

### Claim 7

A device comprising:
a first stack of first semiconductor layers disposed over a substrate, wherein each of the first semiconductor layers of the first stack are separated from each other;
a second stack of second semiconductor layers disposed over the substrate, wherein each of the second semiconductor layers of the second stack are separated from each other;
a first gate structure wrapping around each of the first semiconductor layers of the first stack;
a second gate structure wrapping around each of the second semiconductor layers of the second stack;
a first source/drain feature extending through the first stack of first semiconductor layer to a first depth, the first source/drain feature including a first epitaxial layer and a second epitaxial layer disposed on the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer both include a p-type dopant; and
a second source/drain feature extending through the second stack of second semiconductor layers to a second depth, the second source/drain feature including a third epitaxial layer and a fourth epitaxial layer disposed on the third epitaxial layer, wherein a first ratio of a height of the first epitaxial layer to the first depth of the first source/drain is greater than a second ratio of a height of the third epitaxial layer to the second depth of the second source/drain feature, wherein the third epitaxial layer and the fourth epitaxial layer both include an n-type dopant.

### Claim 8 (depends on 7)

The device of claim 7, wherein a third ratio of a height of the second epitaxial layer to the first depth of the first source/drain is less than a fourth ratio of a height of the fourth epitaxial layer to the second depth of the second source/drain feature.

### Claim 9 (depends on 7)

The device of claim 7, further comprising:
a first sidewall spacer extending from a first one of the first semiconductor layers of the first stack to a second one of the first semiconductor layers of the first stack, the first sidewall spacer physically contacting the first source/drain feature; and
a second sidewall spacer extending from a first one of the second semiconductor layers of the second stack to a second one of the second semiconductor layers of the second stack, the second sidewall spacer physically contacting the second source/drain feature.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first depth and the second depth are substantially the same.

### Claim 11 (depends on 7)

The device of claim 7, wherein the first epitaxial layer extend to the first depth and the third epitaxial layer extends to the second depth, and
wherein the first depth and the second depth are substantially the same.

### Claim 12

A semiconductor device comprising:
a first semiconductor fin over a first region of a substrate and a second semiconductor fin over a second region of the substrate;
a first metal gate structure over the first semiconductor fin and a second metal gate structure over the second semiconductor fin;
a first spacer along a sidewall of the first metal gate structure and a second spacer along a sidewall of the second metal gate structure; and
a first epitaxial feature over the first semiconductor fin and a second epitaxial feature over the second semiconductor fin, wherein the first epitaxial feature includes a first epitaxial layer and a second epitaxial layer formed over the first epitaxial layer, the second epitaxial feature includes a third epitaxial layer and a fourth epitaxial layer formed over the third epitaxial layer, and a first ratio of a height of the second epitaxial layer to a height of the first epitaxial feature is less than a second ratio of a height of the fourth epitaxial layer to a height of the third epitaxial feature, wherein the first epitaxial layer includes a p-type dopant and the third epitaxial layer and the fourth epitaxial layer both include an n-type dopant.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a height of the second epitaxial layer is less than a height of the fourth epitaxial layer.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein a first distance between a sidewall of the first epitaxial feature and a sidewall of the first spacer is greater than a second distance between a sidewall of the second epitaxial feature and a sidewall of the second spacer.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein the first ratio is about 50% to about 80%.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein the second ratio is about 70% to about 90%.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, wherein the first epitaxial layer has a first dopant concentration and the second epitaxial layer has a second dopant concentration greater than the first dopant concentration, and wherein the third epitaxial layer has a third dopant concentration and the fourth epitaxial layer has a fourth dopant concentration greater than the third dopant concentration.

### Claim 18 (depends on 12)

The semiconductor device of claim 12, wherein each of the first semiconductor fin and the second semiconductor fin includes multiple semiconductor layers, and the first metal gate stack wraps around each of the multiple semiconductor layers of the first semiconductor fin and the second metal gate stack wraps around each of the multiple semiconductor layers of the second semiconductor fin.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein the first region is for p-type field-effect transistor (PFET) and the second region is for n-type field-effect transistor (NFET).

### Claim 20 (depends on 12)

The semiconductor device of claim 12, wherein the second epitaxial feature is wider than the first epitaxial feature.