# US 12,112,987 B2 · Semiconductor device with fin end spacer plug and method of manufacturing the same

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- Number: US 12,112,987 B2
- Document ID: US12112987B2
- Status: Granted
- Kind: B2
- Application number: 18/226,185
- Filed: 2023-07-25
- Published: 2023-11-16
- Granted: 2024-10-08
- Earliest claimed: 2018-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tzu-Chung Wang; Tung Ying Lee
- Web page: https://patentgrep.com/patent/US12112987B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.

## Claims

### Claim 1

A semiconductor device, comprising:
a first fin and a second fin each with a fin liner layer, on a substrate;
a fin end spacer plug on end surfaces of the first and second fins;
gate electrodes disposed over the first and second fins, respectively;
a dummy gate electrode over the fin end spacer plug and one of the first or the second fins;
an insulating layer on the first and second fins; and
a source/drain epitaxial layer in a source/drain recess in each of the first and second fins.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising sidewall spacers formed on the first and second fins, wherein the fin end spacer plug and the sidewall spacers are formed of the same material.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the fin end spacer plug has a bottom level below a top surface of the fin liner layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the fin end spacer plug has a bottom level above a top surface of the fin liner layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the source/drain epitaxial layer includes Si—P.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the fin end spacer plug is formed of a material including silicon nitride based material.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the silicon nitride based material includes silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

### Claim 8

A semiconductor device, comprising:
a first fin and a second fin each with a fin liner layer, on a substrate;
a fin end spacer plug on end surfaces of the first and second fins;
gate electrodes disposed over the first and second fins, respectively;
a dummy gate electrode over the fin end spacer plug;
an insulating layer on the first and second fins; and
a source/drain epitaxial layer in a source/drain recess in each of the first and second fins, wherein no gate electrode and no dummy gate electrode are disposed above edges of the first and second fins.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising sidewall spacers formed on the first and second fins, wherein the fin end spacer plug and the sidewall spacers are formed of the same material.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the fin end spacer plug has a bottom level below a top surface of the fin liner layer.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the fin end spacer plug has a bottom level above a top surface of the fin liner layer.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the source/drain epitaxial layer includes Si—P.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the fin end spacer plug shields the source/drain epitaxial layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the fin end spacer plug is formed of a material including silicon nitride based material.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the silicon nitride based material includes silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

### Claim 16

A semiconductor device, comprising:
a first fin and a second fin along a line extending in a first direction and separated from each other;
a fin end spacer plug extending in a second direction perpendicular to the first direction and disposed between ends of the first fin and the second fin;
gate electrodes respectively disposed over the first fin and the second fin; and
a dummy gate electrode disposed over the fin end spacer plug and between the ends of the first fin and the second fin, wherein the dummy gate electrode is separated from the ends of the first and second fins by the fin end spacer plug.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the fin end spacer plug comprises a first layer made of a first material and a second layer made of a second material on the first material, wherein the first material and the second material are different, and wherein the dummy gate electrode is separated from the ends of the first and second fins by the second layer of the fin end spacer plug.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, further comprising an insulating layer on the first and second fins.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein each of the first fin and the second fin is formed on a substrate and comprises a fin liner layer.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, further comprising a source/drain epitaxial layer formed in a source/drain recess in each of the first fin and the second fin.